Commit Graph

37 Commits (3b4aaec9260b074fd3d7869d4691295a0ce4dce0)

Author SHA1 Message Date
Istvan Csomortani 6bbf1ae83c avl_dacfifo: End of burst is not always end of a transaction
The XFER_END state defines the end of a transaction, when the entire
data set is written or read to/from the DDRx memory.
A transaction can contain multiple Avalon bursts. Make sure that the FSM
goes back into staging phase at the end of each burst; also define a
signals which indicate the end of each burst for control.
2017-12-09 09:56:33 +00:00
Istvan Csomortani 960883c789 avl_dacfifo: Fix dac_xfer_req generation
The dac_xfer_req should indicate one single thing, that the FIFO is in
read phase. Should not be affected by any signals, which indicates data
validity on any interface. (e.g. dac_valid)
This signal is not used by the device core, its main purpose is to
indicate the state of the interface for a posible intermediat processing
module.
2017-11-03 09:32:10 +00:00
Istvan Csomortani 572cd10c35 avl_dacfifo: Fix reset architecture in avl_dacfifo_rd
Make sure that all address registers are reset during the initialization
phase of the FIFO.
2017-11-03 09:29:43 +00:00
Istvan Csomortani 17c749962c avl_dacfifo: Fix the loopback of avl_xfer_req
When the read FSM is not in a burst, the incomming avl_xfer_req can be
looped back to the write module.
2017-11-02 12:02:54 +00:00
Istvan Csomortani 610a237730 avl_dacfifo: Fix write enable generation
Data is written into the CDC FIFO if both dma_ready and dma_valid are
asserted. This two signals is enough to validate the data coming from
the DMA.
2017-11-01 12:22:18 +00:00
Istvan Csomortani 6895915076 avl_dacfifo: Fix reset of write address register
Fix the reset of the dma_mem_waddr (write address register of the CDC
FIFO on DMA's clock domain). This solves the occasional invalid read backs after
multiple re-initialization of the PL_DDR_FIFO.
2017-11-01 12:21:56 +00:00
Istvan Csomortani e3ea51ade3 avl_dacfifo: Refactor the fifo
+ Build both the read and write logic around an FSM
 + Consistent naming of registers and wires
 + Add support for burst lenghts higher than one, current burst lenght
is 64
 + Fix all the bugs, and make it work (first bring up with
adrv9371x/a10soc)
2017-10-31 14:30:06 +00:00
Istvan Csomortani 700ed156ab [axi|avl]_dacfifo: Create a separate bypass module for altera/xilinx 2017-09-25 08:56:40 +01:00
Istvan Csomortani deefb33490 avl_dacfifo: Update IP to qsys flow 2017-08-22 09:16:21 +01:00
Istvan Csomortani 7554887982 avl_dacfifo: Fix timing violation
+ Transfer avl_last_beats into dac clock domain
 + Update constraint file
2017-06-07 11:02:44 +01:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani cb8d6830f5 avl_dacfifo: Update constraints 2017-05-25 15:12:16 +03:00
Istvan Csomortani 3ee7ed7375 avl_dacfifo: Cosmetic changes 2017-05-25 15:12:15 +03:00
Istvan Csomortani 154e936a4b avl_dacfifo: Fix issues with avl_dacfifo_wr
+ fix issues with the last partial avalon transfer.
 + fix reset related problems
2017-05-25 15:12:15 +03:00
Istvan Csomortani e34e87e7f8 avl_dacfifo: Add support for partial avalon transfers
By adding support for partial avalon transfers (data width < bus width),
valid data set size (DMA transfer length) will be dependent on the DMA bus
width only.
2017-05-25 15:12:15 +03:00
Istvan Csomortani a993eefe57 avl_dacfifo: Grey coder/decoder integration 2017-05-25 15:12:14 +03:00
Istvan Csomortani 14a058195d avl_dacfifo: Add avl_dacfifo_byteenable_coder
Define and integrate avl_dacfifo_byteenabke_coder module,
which generates the byteenable signal for the avalon interface.
2017-05-25 15:12:14 +03:00
Istvan Csomortani 81fa65cd51 avl_dacfifo: Few cosmetic changes on avl_dacfifo_wr
+ avl_write_transfer_done_s is a redundant net
 + specify the net state explicitly on if statements
 + to define the edge of avl_mem_fetch_wr_address signal,
its register and its second sync register should be used
2017-05-25 15:12:13 +03:00
Istvan Csomortani 398619d866 avl_dacfifo: Add support for MEM_RATIO 32 2017-05-25 15:12:13 +03:00
Istvan Csomortani a1539a62b7 avl_dacfifo: Integrate util_delay into dac_xfer_out path
The ad_mem_asym memory read interface has a 3 clock cycle delay, from the
moment of the address change until a valid data arrives on the bus;
because the dac_xfer_out is going to validate the outgoing samples (in conjunction
with the DAC VALID, which is free a running signal), this module will compensate
this delay, to prevent duplicated samples in the beginning of the
transaction.
2017-05-25 15:12:13 +03:00
Istvan Csomortani 6d52034abb avl_dacfifo: dma_ready was muxed incorrectly 2017-05-25 15:12:12 +03:00
Istvan Csomortani da68705fee avl_dacfifo: Fix the avalon address switch 2017-05-25 15:12:12 +03:00
Istvan Csomortani 04f397f688 avl_dacfifo: Fix a few control signals
+ avl_last_transfer depends on the avl_xfer_req state
  + avl_xfer_req will be asserted after the last avalon write
transfer
2017-05-25 15:12:12 +03:00
Istvan Csomortani 8f9cadb017 avl_dacfifo: Fix the avl_write generation
The asymetric memory has a 3 clock cycle delay on its read
interface, therefor the minimum distance between two consecutive
avalon write should be 3.
2017-05-25 15:12:11 +03:00
Istvan Csomortani 0f1e51ac98 avl_dacfifo: Fix alv_mem_readen generation 2017-05-25 15:12:11 +03:00
Istvan Csomortani f456ebc6f0 avl_dacfifo: Few cosmetic changes on avl_dacfifo_wr
+ all net names should have a *_s postfix
  + avl_burstcount is a constant 1, no need for an additional
register for it
  + all CDC should have two synchronization register, add
avl_last_beat_req_m2
2017-05-25 15:12:11 +03:00
Istvan Csomortani 9a6dc36289 avl_dacfifo: Fix indentation for acl_dacfifo.v 2017-05-25 15:12:10 +03:00
Istvan Csomortani 7666c9f0d2 avl_dacfifo: Add a parameter AVL_ADDRESS_WIDTH 2017-05-25 15:12:10 +03:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Rejeesh Kutty c728299e71 altera- default to latest version 2017-05-12 13:25:17 -04:00
Istvan Csomortani 77eafbcccd avl_dacfifo: Update constarint file 2017-04-25 12:03:46 +03:00
Istvan Csomortani 1ef3fd4668 avl_dacfifo: Fix read/write address switching 2017-04-25 12:03:22 +03:00
Istvan Csomortani 4007df2094 avl_dacfifo: Update constraints 2017-04-21 17:25:46 +03:00
Istvan Csomortani 89b3f45fff avl_dacfifo: Use the ad_mem_asym for altera 2017-04-21 17:25:46 +03:00
Istvan Csomortani b7bfa2d91f avl_dacfifo: Delete redundant file 2017-04-21 17:25:46 +03:00
Istvan Csomortani 180a80493b avl_dacfifo: Initial commit 2017-04-21 13:26:37 +03:00