983e56d72c
ad9963: Remove localparams from module parameter list
...
Declaring local parameters in the module parameter list is not valid
verilog. For some reasons Vivado accepts it nevertheless so the code has
worked so far. But this is not true for other tools, so move the local
parameter definitions inside the module body.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-30 11:40:28 +02:00
1d448f0013
adi_ip: Set up SCOPE_TO_REF for xdc and save the core
2017-03-29 18:40:24 +03:00
ea7e93d27f
fmcomms2: Use the new constriants from 335fef0
2017-03-29 18:36:09 +03:00
335fef0f42
ad_axi_ip_constr: Split up this constraint file into separate files
...
For experimentation, to solve a constraint scoping issue, split up the
ad_axi_ip_constraint file into separate constraints file, in function
of there parent module.
2017-03-29 18:31:40 +03:00
2419b3626b
ad9684- fix sdc typo
2017-03-23 12:49:44 -04:00
ae0f4672b2
daq1/a10gx- fix project to compile
2017-03-23 09:46:40 -04:00
8063ba2b66
make updates
2017-03-20 16:05:18 -04:00
c277b39796
arradio/c5soc- critical warnings fix
2017-03-20 12:14:13 -04:00
cd0701513a
axi_logic_analyzer: Added an additional delay to the trigger, to be similar with the analog path
2017-03-14 18:00:42 +02:00
3c7f73a880
axi_dmac: Fix dummy port enablement dependency
...
It seems that in the latest version a constant of "0" is no longer a valid
enablement dependency and "false" has be used instead.
Not setting the enablement dependency correctly results in the AXI port to
be assumed to be read-write rather than just read or write. This will
generate unnecessary logic for example in interconnects to which the DMA
controller is connected.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-14 16:03:25 +01:00
d7edd71aef
axi_logic_analyzer: Triggering changes on valid data
2017-03-14 15:25:00 +02:00
1ef064ac03
axi_ad9361- add receive init delay
2017-03-13 16:28:38 -04:00
b0e88eb5ff
axi_ad9361- add receive init delay
2017-03-13 16:28:24 -04:00
0ae79ca7ac
move/rename - delay script belongs to ad9361
2017-03-10 12:44:32 -05:00
ce6b0cc7f3
util_fir_dec: Changed output rounding mode to Symmetric rounding to Zero
...
This removes the added DC component that was introduced by the previous rounding mode
2017-03-09 16:33:17 +02:00
eb946b54cc
util_fir_int: Shifted data so that the amplitude at the output of the filter is the same with the input
2017-03-08 14:29:26 +02:00
660dddf1e8
util_dacfifo: Define constraints for bypass
2017-03-07 16:14:46 +02:00
7559d23873
util_dacfifo/constraints- false paths for bypass
2017-03-06 10:33:07 -05:00
7478777d8d
axi_dacfifo: Match the ports with util_dacfifo
2017-03-03 18:46:16 +02:00
760228d676
util_dacfifo: Update the util_dacfifo
...
Fix bypass and undate the general functionality. If bypass enabled
the FIFO will function as a normal CDC FIFO.
2017-03-03 18:43:36 +02:00
e0d4607692
adcfifo- asym_mem primitive changes
2017-03-01 15:55:56 -05:00
3586397f57
altera/common- add asymmetric fifo
2017-03-01 15:35:04 -05:00
9c65166e26
ad9371- missing net declarations
2017-02-28 13:31:23 -05:00
104e9dfcdc
adc/dac-fifo altera cores
2017-02-28 13:30:50 -05:00
0d231935ef
library/util_dacfifo- match bypass port with axi_dacfifo
2017-02-27 16:06:39 -05:00
1d6ddacfd6
axi_ip_constr: Fix constraints
...
The filter for CDC registers were too generic, and a few non-CDC
register were set as asynchronous register.
2017-02-27 16:25:09 +02:00
1c8e63cb68
axi_adc_trigger: Added triggered register
2017-02-27 14:26:19 +02:00
37a1c98c12
axi_logic_analyzer: Switched from BUFGMUX to BUFGMUX_CTRL for glitch free clock switching
2017-02-27 14:19:54 +02:00
11623e79be
axi_dacfifo: Fix clock for read address generation
2017-02-24 15:47:04 +02:00
3e596347fd
axi_dacfifo: Delete unused wires
2017-02-24 15:45:51 +02:00
ac2e5a9dac
constraints: Update constraints
...
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
f326c03ff3
axi_dacfifo: Define constraint for bypass
...
The bypass module currently is supported, when the DMA data width
is equal with the DAC data width.
The dac_data output is enabled with dac_valid.
2017-02-24 12:35:42 +02:00
b9d3039568
axi_dacfifo: Register the dac_valid signals
2017-02-24 12:34:58 +02:00
debc6e2066
axi_dacfifo: Data from DMA is validated with dma_ready too
2017-02-24 12:32:25 +02:00
dfcd5214a0
axi_dacfifo: axi_dvalid should come from dacfifo_rd module
2017-02-24 12:28:46 +02:00
6b90054343
axi_ad9361: Define CDC constraint for tdd_sync
2017-02-24 11:24:07 +02:00
1fce57f6c3
axi_dacfifo: Redesign the bypass functionality
2017-02-23 17:32:31 +02:00
573959c826
Makefiles: fixed axi_adxcvr/util_adxcvr Makefiles to include interfaces dependancy
2017-02-23 16:16:34 +02:00
d820d3d245
util_sync_constr: Preserve 1bit CDCs with ASYNC_REG true
2017-02-23 11:44:01 +02:00
94bda1d415
axi_ad9361: Preserve 1bit CDCs with ASYNC_REG true
2017-02-23 11:43:10 +02:00
2da7dd4079
axi_ip_constr: Update constraints
...
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-23 11:33:25 +02:00
2b354af876
axi_ad9361_tdd: Register the tdd_sync_cntr output
2017-02-23 11:31:23 +02:00
e3ac341aad
axi_dacfifo: Fix constraints
2017-02-21 14:45:18 +02:00
981a61bf16
axi_dacfifo: Clean up the axi_dacfifo_wr.v module
2017-02-17 18:40:02 +02:00
f10866e4c3
axi_*fifo: Delete/replace AXI_BYTE_WIDTH parameter
2017-02-16 19:54:41 +02:00
95a4ea20c8
axi_dacfifo: Delete redundant parameter BYPASS_EN
2017-02-16 19:53:44 +02:00
358aa48c76
axi_adc_decimate: Fix assignment width
2017-02-15 11:38:43 +02:00
c6ee76421b
axi_usb_fx3: Fixed clock domain association
2017-02-14 11:48:07 +02:00
7c86b038ef
util_fir_int: manually request data at 1/8 clock frequency
2017-02-13 18:05:59 +02:00
5fa6dba333
Make: Update Makefiles
2017-02-10 16:32:58 +02:00
0dae754f2d
axi_adxcvr: Add rparam register to Altera XCVR
2017-02-10 16:19:17 +02:00
24daffcf5c
spi_engine: Set up default driver value for input ports
2017-02-07 12:30:46 +02:00
47db0d80fe
axi_ad7616: Set up default driver value for input ports
2017-02-07 12:29:21 +02:00
a57fb5f82f
library/ad9122- constraints clean-up
2017-02-02 14:21:41 -05:00
1e54b5230f
axi_adxcvr- add m_axi associated clock
2017-02-02 11:17:56 -05:00
806d19febc
axi_adxcvr- add primitive info read
2017-02-01 13:38:29 -05:00
1c9d8c4e7c
axi_adxcvr- add primitive info read
2017-02-01 13:35:02 -05:00
1df6178ab8
library: Update common Makefile
2017-01-31 16:44:32 +02:00
7387df9d13
util_var_fifo: Initial commit
2017-01-31 16:26:45 +02:00
b9c94f63a5
util_extract: Initial commit
2017-01-31 16:26:05 +02:00
6604cc7322
axi_logic_analyzer: Initial commit
2017-01-31 16:23:56 +02:00
9c975211da
axi_dac_interpolate: Initial commit
2017-01-31 16:22:49 +02:00
4a7232cbcb
axi_adc_decimate: Initial commit
2017-01-31 16:21:39 +02:00
35b97abc6d
axi_adc_trigger: Initial commit
2017-01-31 16:20:13 +02:00
fb945ac51c
axi_ad9963: Initial commit
2017-01-31 16:18:58 +02:00
d5af828b9c
Merge branch 'dev' into hdl_2016_r2
2017-01-30 17:10:05 +02:00
db924953bb
altera- warnings about init values
2017-01-30 10:01:28 -05:00
eb8a3fff3c
axi_dmac: Set IP core name and description
...
Add a human readable name and descriptor for the AXI DMAC core.This string
will appear in various places e.g. like the IP catalog. This is a purely
cosmetic change.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-01-30 13:58:48 +01:00
3dd736fe8c
axi_dmac: Add identification register
...
Add a register to the AXI DMAC register map which functions has a
identification register. The register contains the unique value of "DMAC"
(0x444d4143) and allows software to identify whether the peripheral mapped
at a certain address is an axi_dmac peripheral.
This is useful for detecting cases where the specified address contains an
error or is incorrect.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-01-30 13:58:48 +01:00
3f3a8bd267
library: forced ad_mem module to be implemented in BRAM for Xilinx devices
2017-01-25 18:12:04 +02:00
c8b638e182
ad9152- add prbs generators
2017-01-23 10:31:57 -05:00
a2b2ebbed2
ad_lvds_in- ultrascale/ultrascale+ sim device mess
2017-01-21 20:54:21 -05:00
afcd11da87
adxcvr- add parameters for xcvr config
2017-01-19 12:40:26 -05:00
746b97dd96
xilin/axi_adxcvr: Fix clock and reset nets[C
2017-01-19 15:46:16 +02:00
57bd6acd0f
library: Update make file
2017-01-19 15:27:31 +02:00
d3ed417f49
axi_adxcvr: Update the packaging script to fix infer mm issues
...
- Change the clock and reset port name of the AXI slave interface
to s_axi_aclk and s_axi_aresetn. This way we can use the adi_ip_properties
process to infer the interface.
- Define an address space reference to the m_axi interface.
2017-01-19 15:16:04 +02:00
7a7a294865
axi_dmac: Fix memory map infer issues
...
Define an address space reference to the m_dest_axi and
m_src_axi interfaces.
2017-01-19 15:09:07 +02:00
a7bd4e6e82
scripts/adi_ip: Update the adi_ip_properties process
...
- Add a process, which automaticaly infer AXI memory mapped
interfaces (adi_ip_infer_mm_interfaces)
- Add missign line breaks to the 'set_propery supported_families'
command
- Fix the deletion of pre-infered memory maps
2017-01-19 15:06:47 +02:00
61afd106b5
util_clkdiv: Keep as valid only settings common for 7Series and Ultrascale
2017-01-18 11:56:24 +02:00
61ee24f26a
util_clkdiv: Make the clock division parametrizable and changed C_SIM_DEVICE to SIM_DEVICE
2017-01-16 14:37:26 +02:00
4b2602437f
util_clkdiv: Added Ultrascale support and switch to BUFGMUX_CTRL for glitch free switching
2017-01-13 13:54:07 +02:00
1f7d19688a
Update Makefile
2017-01-12 15:58:32 +02:00
b59549053c
scripts/adi_ip: Fix adi_ip_infer_interfaces process
...
This patch is a complementary fix of 8b8c37 patch. And fix
all the 'infer interface' issues.
The adi_ip_infer_interfaces process was renamed to
adi_ip_infer_streaming_interfaces. Now the process just do
what its name suggest.
Affected cores were axi_dmac, axi_spdif_rx, axi_spdif_tx, axi_i2s_adi
and axi_usb_fx3. All these cores scripts were updated.
2017-01-12 12:15:33 +02:00
9b29941c77
util_clkdiv: Add constraint file
2017-01-11 18:11:53 +02:00
c78c9cf633
util_fir_int: Updated coefficient file
2016-12-21 10:06:56 +02:00
c0a2ef1ac4
library- altera power up warnings
2016-12-20 16:18:15 -05:00
ce47cf8d30
ad_sysref_gen: Fix sysref generation
...
Toggle sysref output just if the sysref_en is asserted.
2016-12-19 18:02:49 +02:00
a228c05bd3
common: Add a SYSREF generation module
...
The SYSREF generator is using a simple free running counter,
which runs on the JESD204 core clock. The period can be
configured using a parameter, it must respect the constraints
defined by the JESD204 standard.
The generator can be enabled through a GPIO line.
2016-12-17 11:12:10 +02:00
596d0fa3fb
axi_ad9122: Add a constraint for a false path
2016-12-16 12:07:40 +00:00
a00d9870be
axi_ip_constr: Fix constraints
...
Modify a contraint for a false path, so it will be applied to
up_delay_cntr module too.
2016-12-16 12:01:38 +00:00
99f72a9b3b
util_gtlb: this core is obsoleted
...
The util_gtlb core is obsoleted by xilinx/axi_xcvrlb
2016-12-12 14:23:47 +02:00
5c8dde8483
util_jesd_gt: this core is obsoleted
...
The util_jesd_gt core is obsoleted by xilinx/util_adxcvr and altera/avl_adxcvr
2016-12-12 14:15:38 +02:00
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
854cd44026
ad9671- xcvr interface changes
2016-12-08 16:05:23 -05:00
977e6d9189
adi_ip_alt: Fix some typo
2016-12-06 15:24:21 +02:00
7876c8ffa4
axi_ad9684: Add loaden and phase ports for altera support
2016-12-06 15:24:20 +02:00
a7d3df8757
axi_ad9684: Update hw tcl script for altera
2016-12-06 15:24:20 +02:00
b0a5be8565
axi_ad9122: Add loaden port for altera support
2016-12-06 15:24:20 +02:00
cedca30cd6
axi_ad9122: Update hw tcl script for altera
2016-12-06 15:24:19 +02:00
0715c962f1
altera/ad_serdes: Fix net alignment for rx_out at ad_serdes_in
2016-12-06 15:24:19 +02:00
Lars-Peter Clausen
Istvan Csomortani
Rejeesh Kutty
Adrian Costina