8ba86cb75c
axi_logic_analyzer: Allow changing data pins direction to output only after data is available from the DMA or if the output is set from a register for that specific pin
2017-04-18 12:17:40 +02:00
8476d9d59a
axi_logic_analyzer: Allow only data[0] to be used as alternative clock.
...
- drive all logic on clk_out instead of clk
2017-04-18 12:17:39 +02:00
c1bdfca4c3
library: Delete all adi_ip_constraint process call
2017-04-06 12:36:47 +03:00
cd0701513a
axi_logic_analyzer: Added an additional delay to the trigger, to be similar with the analog path
2017-03-14 18:00:42 +02:00
d7edd71aef
axi_logic_analyzer: Triggering changes on valid data
2017-03-14 15:25:00 +02:00
37a1c98c12
axi_logic_analyzer: Switched from BUFGMUX to BUFGMUX_CTRL for glitch free clock switching
2017-02-27 14:19:54 +02:00
ac2e5a9dac
constraints: Update constraints
...
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
6604cc7322
axi_logic_analyzer: Initial commit
2017-01-31 16:23:56 +02:00
Adrian Costina
Istvan Csomortani