Commit Graph

109 Commits (3a4581a8df70e49f0ea345e42ccc72f15393f898)

Author SHA1 Message Date
Istvan Csomortani 9f7fff2d2f axi_ad9361/tdd: Add new control signals to the TDD data flow control logic
Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 14:10:49 +03:00
Rejeesh Kutty 6e3817d419 axi_jesd_xcvr: individual reset control 2015-07-13 10:04:34 -04:00
Rejeesh Kutty b25b2e3020 registers for signal tap 2015-07-08 15:47:45 -04:00
Rejeesh Kutty ea2bd71904 synchronize up signals separately 2015-07-07 12:51:13 -04:00
Rejeesh Kutty c1fcbeec8e library/axi_jesd_xcvr: interface name matching 2015-07-07 10:21:53 -04:00
Rejeesh Kutty 3a5da47239 xcvr- initial checkin 2015-07-06 13:51:55 -04:00
Lars-Peter Clausen cf6052e2a8 axi_hdmi_tx: Add control to bypass chroma sub-sampler
Add a control bit to the register map that allows to bypass the chroma
sub-sampler in the axi_hdmi_tx core. This is primarily interned to be used
to send the test-pattern directly to the HDMI transmitter without modifying
it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 21:16:09 +02:00
Lars-Peter Clausen d6c64e031f axi_hdmi_rx: Drop TPG enable from register map
The TPG is no longer part of the RX core and the corresponding bit in the
register map isn't hooked up to anything. So drop it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
Lars-Peter Clausen 542d64bb5a up_hdmi_rx: Fix enable control
Connect the enable signal in the register map to the up_preset signal so
that it is possible to enable/disable to core at runtime.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
Lars-Peter Clausen 231a21548c up_hdmi_rx: Fix TPM OOS clear
The TPM OOS status flag is in bit 1. Make sure writing to bit 1 rather than
bit 0 clears the TPM OOS.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
Rejeesh Kutty 185e489802 cpack- signaltap mess 2015-06-29 16:31:53 -04:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Rejeesh Kutty ac6e28c461 library/common: add altera signaltap 2015-06-19 14:33:01 -04:00
Istvan Csomortani ddc08c960c ad_tdd_control: Connect the reset to all the flops 2015-06-11 12:07:47 +03:00
Rejeesh Kutty e2f4a4c5cf library: make preset registered for timing paths 2015-06-10 13:41:41 -04:00
Istvan Csomortani c926daca3a ad9361/tdd: Fix generation of tx_valid_* signals
In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
2015-06-08 16:22:21 +03:00
Istvan Csomortani 2e877389b2 ad9361_tdd: Some naming and hierarchical changes 2015-06-04 18:09:49 +03:00
Istvan Csomortani 3b1ea7e528 axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch
598ece4c8d
2015-06-04 18:09:47 +03:00
Rejeesh Kutty 6548bcd71f axi_ip- constraints: add rst path 2015-06-04 10:53:13 -04:00
Rejeesh Kutty e7470036bf library- drp moved to up clock 2015-06-01 13:39:26 -04:00
Rejeesh Kutty aa24c442f5 a10gx- no-ddr 2015-06-01 11:00:01 -04:00
Rejeesh Kutty 92fc0e050d altera- common sdc 2015-06-01 10:59:57 -04:00
Adrian Costina 83df53d9bf adc_common: Updated version because the delay registers have been changed 2015-05-25 17:18:14 +03:00
Adrian Costina 1ef83bd88b axi_ad9671: Updated port names. Fixed synchronization of the rx_sof with the ad_jesd_align module, so that data valid is assigned correctly 2015-05-23 00:16:27 +03:00
Istvan Csomortani 660c84e01c axi_ad9434 : Update the IO delay interface 2015-05-22 19:47:09 +03:00
Rejeesh Kutty 0c6ef203c0 iobuf: do is a system-verilog keyword 2015-05-21 14:06:13 -04:00
Rejeesh Kutty 9762c65868 library- jesd-align port name change 2015-05-20 14:25:21 -04:00
Rejeesh Kutty 6e047f78c6 delay-cntrl: up-clk, direct access + tx 2015-05-18 14:28:20 -04:00
Istvan Csomortani a07d11c3e9 axi_ad9361_tdd: Define control bits for continuous receive/transmit 2015-05-14 17:21:32 +03:00
Istvan Csomortani 7c9bc40c75 axi_ad9361&TDD: Update TDD
+ Delete unnecessary registers
+ Add the module ad_addsub.v to resolve additions and subtractions inside TDD control
+ Redefine the burst logic
+ Redesign the control signal generations
+ Note: This patch fix the TDD related timing violations
2015-05-13 14:03:01 +03:00
Istvan Csomortani 2e7135c3c2 axi_ad9361_tdd: Initial commit.
Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 12:20:44 +03:00
Adrian Costina d623f77453 axi_jesd_gt: Added rx_jesd_rst and tx_jesd_rst.
Resets for both up clock domain and rx clock domain are needed in some projects
2015-04-30 12:07:36 +03:00
Adrian Costina a7a2d194e9 axi_jesd_gt: Switched rx_rst and rx_rst_done to up clock domain, to be compatible with xilinx JESD core 2015-04-28 15:04:18 +03:00
Lars-Peter Clausen 7c97e192f2 dma_fifo: Simplify FIFO WE condition
The only time we must not write to the FIFO is when it is full as this will
overwrite the first sample.  Under all other conditions it is ok to write
data. If that data is invalid it will be overwritten when valid arrives.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-16 17:48:22 +02:00
Lars-Peter Clausen b14721b8ae library: Use common prefix for CDC signal names
Use a common naming scheme for CDC signals to make it easier to create
constraints for them.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:22 +02:00
Istvan Csomortani e116822059 imageon_zc706: Updates and fixes
+ sync the sof to the dma_de signal
+ hdmi_rx_dma is connected to the HP1
+ fix syncronization signal in the CSC module
+ hdmi_rx_clk is asynchronous
2015-03-27 18:57:32 +02:00
Rejeesh Kutty 552d9b41f7 imageon: updates 2015-03-24 15:08:48 -04:00
Rejeesh Kutty b29e97f985 hdmi_rx: imageon updates 2015-03-24 15:08:48 -04:00
Istvan Csomortani 80c2a5a45d axi_hdmi_rx: General clean up 2015-03-23 12:39:26 +02:00
Rejeesh Kutty 8dfcbdfd48 gt_channel/gt_common: simulation parameter warning fix 2015-03-06 12:36:07 -05:00
Rejeesh Kutty 57e1f0e334 gt_channel/gt_common: simulation parameter warning fix 2015-03-06 12:36:03 -05:00
Rejeesh Kutty 2d01955042 up_gt: change version dfe/lpm support 2015-03-05 09:47:16 -05:00
Istvan Csomortani 1613f7fb41 cftl_cip: Add util_pmod_fmeter IP to library
Frequency meter IP for CN0332.
2015-02-23 17:20:12 +02:00
Rejeesh Kutty 2442b6e929 gt- report device type 2015-02-17 11:43:50 -05:00
Rejeesh Kutty de043ce130 gt_channel: lpm/dfe programmable 2015-02-13 11:33:04 -05:00
Rejeesh Kutty 870ebdb562 up_gt: support lpm mode 2015-02-12 16:21:11 -05:00
Rejeesh Kutty 1e7c9a3924 gt_es: support lpm mode - 2/2 2015-02-12 16:20:43 -05:00
Rejeesh Kutty 0a8e6f62ef gt_es: support lpm mode - 1/2 2015-02-12 15:15:18 -05:00
Rejeesh Kutty 9e2e2ef44e xfer-logic: stretch toggles to allow capture 2015-02-06 22:15:16 -05:00
Rejeesh Kutty e9231c8f36 xfer-logic: stretch toggles to allow capture 2015-02-06 22:15:14 -05:00