pluto_hdl_adi

Commit Graph

Author	SHA1	Message	Date
Sergiu Cuciurean	da6d9da4f0	projects: cn0540: coraz7s: Add XADC support The coraz7s has an Arduino/chipKIT Shield connector with 6 Single-ended and 8 Differential Analog inputs tied to Xilinx's XADC. The CN0540 uses the A0-5 pins as single-ended ADC channels to monitor the differential input, ADC driver, and buffer voltages. Signed-off-by: Sergiu Cuciurean <sergiu.cuciurean@analog.com>	2020-10-02 11:14:21 +03:00
Istvan Csomortani	dae1de0405	cn0540/bd: Generate a 80MHz spi_clk Generate a higher frequency of spi_clk using an axi_clkgen. (MMCM) CAUTION: ad7768-1 is still violating the standard SPI timing, reducing the timing window significantly for the last bit (or last high bit).	2020-10-02 10:50:06 +03:00
Stanca Pop	193fce338d	cn0540: Initial commit	2020-05-28 18:49:35 +03:00

Author

SHA1

Message

Date

Sergiu Cuciurean

da6d9da4f0

projects: cn0540: coraz7s: Add XADC support

The coraz7s has an Arduino/chipKIT Shield connector with 6 Single-ended
and 8 Differential Analog inputs tied to Xilinx's XADC.
The CN0540 uses the A0-5 pins as single-ended ADC channels to monitor
the differential input, ADC driver, and buffer voltages.

Signed-off-by: Sergiu Cuciurean <sergiu.cuciurean@analog.com>

2020-10-02 11:14:21 +03:00

Istvan Csomortani

dae1de0405

cn0540/bd: Generate a 80MHz spi_clk

Generate a higher frequency of spi_clk using an axi_clkgen. (MMCM)

CAUTION: ad7768-1 is still violating the standard SPI timing,
reducing the timing window significantly for the last bit (or last high
bit).

2020-10-02 10:50:06 +03:00

Stanca Pop

193fce338d

cn0540: Initial commit

2020-05-28 18:49:35 +03:00

3 Commits (38f3627695927c15e2ec0878dc3996d183fcc022)