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991 Commits (3871d3ce2b28a0198e178d5e70ea9b0a6f74634e)

Author SHA1 Message Date
Rejeesh Kutty 3871d3ce2b ad9361-c5/a10 - updates 2016-05-09 13:54:08 -04:00
Rejeesh Kutty 9cd6e2da51 quartus-mess- altddio direct instantiation 2016-05-09 13:54:08 -04:00
AndreiGrozav 726ddb6e93 ad_lvds_clk: Fixed assignment mismatched 2016-05-09 10:32:18 +03:00
Istvan Csomortani b0538a03a2 Make: Update 2016-05-06 16:44:24 +03:00
AndreiGrozav b36c722ec9 up_hdmi_tx: Discard the standard default values 
Restore the base functionality of the core. Changing the data format
will not set by default its standard maximum and minimum data clipping
ranges.
 2016-05-05 13:41:46 +03:00
AndreiGrozav 68d83def01 axi_hdmi_tx_core: Fixed data path 2016-05-05 13:32:25 +03:00
AndreiGrozav 0d2dc2c62b axi_hdmi_tx: Fixed data bus width 2016-05-05 13:26:59 +03:00
Rejeesh Kutty bdfa383622 library/axi_ad9361: tdd false paths 2016-05-04 13:42:12 -04:00
Rejeesh Kutty ef6c99ecab library/axi_ad9361: hw component updates 2016-05-04 13:42:12 -04:00
Rejeesh Kutty 3b5e44e37d library/axi_ad9361: mmcm rst for plls 2016-05-04 13:42:12 -04:00
Rejeesh Kutty 16a13b2023 library/axi_ad9361: add rst/locked to clock 2016-05-04 13:42:11 -04:00
Rejeesh Kutty 1aac44b0d9 library: ad_*clk- rst/locked 2016-05-04 13:42:11 -04:00
Rejeesh Kutty d82ca5dc3c library/common- altera variations 2016-05-04 13:42:11 -04:00
AndreiGrozav b6b68e9ab7 axi_jesd_gt: Split the constraint file 
-split axi_jesd_gt_constr.xdc file in rx, tx and common constraint files
-updated tcl script
 2016-05-04 19:32:06 +03:00
Rejeesh Kutty 385ed31a45 make files update 2016-04-29 10:17:35 -04:00
Rejeesh Kutty 3f5e1e1203 ad9361- dev_if module name change 2016-04-29 10:17:35 -04:00
Rejeesh Kutty 89f5d2394e altera- clock variations 2016-04-29 10:17:35 -04:00
Rejeesh Kutty 243d3e6e41 ad9361- a10soc sdc files 2016-04-29 10:17:35 -04:00
Rejeesh Kutty aa2aa902bf ad9361- a10soc updates 2016-04-29 10:17:35 -04:00
Rejeesh Kutty f411d29e30 ad9361- a10soc changes 2016-04-29 10:17:35 -04:00
Rejeesh Kutty 3563c2212c common/altera- removed dcfilt/mul 2016-04-29 10:17:35 -04:00
Rejeesh Kutty 0260280db1 common/altera- data path 2016-04-29 10:17:35 -04:00
Rejeesh Kutty ed62101308 common/altera: primitives 2016-04-29 10:17:35 -04:00
Rejeesh Kutty 779d014750 ad9361-common alt/xil interface 2016-04-29 10:17:35 -04:00
Rejeesh Kutty e9b199959a library/adcfifo- constraints update 2016-04-20 15:57:25 -04:00
AndreiGrozav 679d471d75 Merge branch 'hdl_2016_r1' into dev 
hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
 2016-04-19 18:05:50 +03:00
Adrian Costina d7d8b2cf1c axi_usb_fx3: Integrated actual GPIF II interface, with 2 address lines 2016-04-19 14:38:26 +03:00
Istvan Csomortani e855ef38f4 axi_dacfifo: Initial commit 
AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
 2016-04-19 11:28:33 +03:00
Istvan Csomortani 42cd05ab19 ad_mem_asym: Add support for more ratios. 
Supported ratios: 1:1/1:2/1:4/1:8/2:1/4:1/8:1
 2016-04-19 11:18:30 +03:00
AndreiGrozav 6fe41ebb08 axi_hdmi_tx: Upgrade hdmi clipping process 
-added two registers that control the clipping ranges (0x01a and 0x01b)
-extend clipping process for all output data formats
 2016-04-12 22:01:07 +03:00
Istvan Csomortani 69d721526a util_dacfifo: Add constraints file 2016-04-12 13:21:50 +03:00
Istvan Csomortani 255b0ebd40 util_dacfifo: Add dac_xfer_out control 
The dac_xfer_out control signal is asserted while the DAC reads back data. Should be connected to upack/dma_xfer_in.
 2016-03-29 16:50:00 +03:00
AndreiGrozav b31cdac6bd util_gmii_to_rgmii: Updated to 2015.4 
The Xilinx interface changed its name from gmii_rtl_1 to gmii_rt_1
 2016-03-23 10:14:18 +02:00
Rejeesh Kutty 46eddd04be library: port updates on mmcm 2016-03-22 12:50:59 -04:00
Rejeesh Kutty de4da6726b axi_clkgen: port updates on mmcm 2016-03-22 12:50:59 -04:00
Rejeesh Kutty 74408881c6 axi_ad9122: optional clock out control 2016-03-22 12:50:59 -04:00
Rejeesh Kutty 65b2e51958 common/mmcm: add another clock 2016-03-22 12:50:59 -04:00
AndreiGrozav 769fecbe00 axi_i2s_adi: Fixed clock association 2016-03-21 20:18:45 +02:00
Istvan Csomortani 373481360b util_dacfifo: Add a bypass option to the FIFO 2016-03-21 14:14:43 +02:00
AndreiGrozav 6d277733d5 axi_spdif_rx: Fixed the clock association 2016-03-18 13:58:13 +02:00
AndreiGrozav 28990e362a axi_spdif_tx: Fixed the clock association 2016-03-18 13:31:06 +02:00
Istvan Csomortani 896c734792 Revert "foobar" 
This reverts commit a3cb8cac45.
 2016-03-18 13:23:02 +02:00
Istvan Csomortani a3cb8cac45 foobar 2016-03-18 11:51:13 +02:00
AndreiGrozav 9b2a106aa0 axi_jesd_gt: changed clock and reset naming to be consistent with the other projects 2016-03-15 11:20:31 +02:00
AndreiGrozav 06b7916303 axi_spdif_tx: changed adi_ip_properties_lite to adi_ip_properties, so that the axi interface can be inferred 2016-03-15 10:18:25 +02:00
AndreiGrozav ef05642e26 axi_spdif_rx: changed adi_ip_properties_lite to adi_ip_properties, so that the axi interface can be inferred 2016-03-15 10:14:05 +02:00
AndreiGrozav b3ed38107c axi_i2s_adi: changed adi_ip_properties lite to adi_ip_properties, so that the axi interface can be inferred 2016-03-15 10:12:45 +02:00
Rejeesh Kutty 8ecf5edaf8 ad9122- pat modes 2016-03-14 11:14:29 -04:00
AndreiGrozav 31cc91d1b9 adi_ip: Updated to 2014.4.2 
- automatically infer clocks, resets, axim_mm and axis interfaces
 2016-03-14 15:14:18 +02:00
Adrian Costina 33b265a742 Makefile: Update Makefiles 2016-03-14 09:31:17 +02:00