0680e44330
system_id: deployed ip
2019-08-06 16:53:11 +03:00
de510b45ab
base: Add system_processor_rst for all the global clocks
2019-06-11 18:13:06 +03:00
20c714eccf
common: Define three global clock nets
...
For all the Xilinx base design, define three global clock nets, which
are saved in the following three global variable: $sys_cpu_clk, $sys_dma_clk
and $sys_iodelay_clk.
These clock nets are connected to different clock sources depending of
the FPGA architecture used on the carrier. In general the following
frequencies are used:
- sys_cpu_clk - 100MHz
- sys_dma_clk - 200MHz or 250Mhz
- sys_iodelay_clk - 200MHz or 500Mhz
2019-06-11 18:13:06 +03:00
660f66af98
kcu105: Moved to smartconnect
2019-04-15 17:49:11 +03:00
ebae8bf8c1
Remove interrupts from system_top for all xilinx projects
...
- remove interrupts from system_top
- for all suported carriers:
- remove all interrupt bd pins
- connect to GND all initial unconnected interrupt pins
- update ad_cpu_interrupt procedure to disconnect a interrupt from GND
before connectiong it to another pin.
2018-08-10 10:10:58 +03:00
71394ee465
kcu105: ip automatic version update
2017-04-18 11:59:54 +03:00
be1328c55b
kcu105- added missing ethernet configurations
2017-01-23 10:14:09 -05:00
fb287d0178
kcu105- updates to match xilinx trd
2016-12-08 09:32:33 -05:00
16ad0f4379
kcu105- 2016.2 update
2016-08-11 10:00:41 -04:00
285059aed0
kcu105: Don't use phy reset automation, as it's not supported for KCU105
2016-08-09 10:19:57 +03:00
452d4706d3
kcu105: Update base project to 2015.4.2
...
- change part to revision 1.1 of the board
2016-08-09 10:19:36 +03:00
d10dd78094
kcu105: Update common design to 2015.4
2016-05-27 14:59:28 +03:00
b555be25d5
kcu105: Update common design to 2015.4
2016-03-18 15:22:42 +02:00
f6e64e42b0
kcu105: add ethernet idelaycntrl
2016-02-26 13:19:49 -05:00
77e2eb7364
projects/common: Fix parameter name for xilinx core axi_gpio
...
Parameter C_GPDATA_WIDTH is changed to C_GPIO_WIDTH.
2015-08-25 10:07:11 +03:00
d3e090da3d
projects/common: Upgrade Xilinx's IP cores
...
To update the projects to Vivado 2015.2 the following IP cores were upgraded:
+ microblaze 9.4 to microblaze 9.5
+ axi_ethernet 6.2 to 7.0
+ mig 6.1 to 7.0
2015-08-25 10:03:49 +03:00
203d7cb470
projects/common: Cosmetic changes.
2015-08-25 09:58:32 +03:00
57cfb7cfb1
hdl/library: Update the IP parameters
...
The following IP parameters were renamed:
PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
d7993401e6
kcu105/adv7511: moved hdmi/spdif out of base design
2015-03-10 16:15:14 -04:00
b31d9abd91
kcu105: gpio/spi moved to base design
2015-03-09 16:04:09 -04:00
1db5f4696f
kcu105: isolate ddr-300M from interconnect-100M timing
2015-03-06 12:37:31 -05:00
7bf4141a3f
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
bf1388b05e
kcu105: rev.d changes
2015-03-04 12:43:04 -05:00
b0b4bfe531
kcu105-daq2-2014.4-- intermediate fixes
2015-01-13 13:40:17 -05:00
7e18162632
projects/common/kcu105/kcu105_system_bd: Restore axi_ethernet SupportLevel 0
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-05 14:48:37 +01:00
3cc890e604
projects/common: KCU105 VC707 update and sync axi_ethernet:6.1 features
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-04 09:49:09 +01:00
3bc9b25e96
projects/common: KCU105 VC707 KC705 sync microblaze core defaults
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-04 09:47:02 +01:00
2d9a529ab8
kcu105: ddr - 800M
2014-11-06 16:50:37 -05:00
f83622a2e6
daq2/kcu105: interrupt updates
2014-10-28 15:51:42 -04:00
a870603db5
common_bd: Update the common block designs to the new IRQ path
...
Avoid the use of xil_concat module by using the ad_interrupts.
2014-10-27 19:44:25 +02:00
d1e3993bd0
kcu105: daq2 updates
2014-10-27 09:59:56 -04:00
43cdafe1e2
kcu105: iic-rstn removed
2014-10-22 16:33:52 -04:00
14ccdaaa78
kcu105: removed spdif reset
2014-10-17 14:00:00 -04:00
e73b3b52dc
kcu105: ethernet fix
2014-10-17 13:47:50 -04:00
7d3be14ab5
common: Connect audio clkgen reset
...
While we are at it also hide the unused locked pin.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:44:46 +03:00
fd89458708
common: Set cpu interconnect strategy to minimize area
...
There will rarely be concurrent access to the peripheral control bus
interconnect, so there is no need to optimize for performace. Setting the
interconnect strategy to minimize area can reduce the resource usage by
~90%.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:43:54 +03:00
cd42345324
projects/common/xxx/xxx_system_bd.tcl: 'Update microblaze defaults
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-10-07 09:17:24 +02:00
fb5d212370
daq2/kcu105: fixed timing violations
2014-09-19 15:55:42 -04:00
41cc92ef49
Remove BASEADDR/HIGHADDR parameters
...
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
b58e425b44
daq2/kcu105: timing improvement -register slices hang
2014-09-08 10:24:56 -04:00
b481df0b5f
library: local constraints async groups
2014-08-14 15:09:51 -04:00
663588eeaf
daq2/kcu105: working ddr version
2014-07-29 09:15:30 -04:00
db2386a351
daq2/kcu105: latest mig updates
2014-07-23 16:25:55 -04:00
cf56a568c6
kcu105: GTH updates
2014-06-05 14:27:38 -04:00
3ac1da178e
kcu105: sane except for ddr4/ethernet
2014-05-06 15:39:05 -04:00
a10043c4f4
kcu105: base complete with ethernet errors
2014-04-30 14:41:43 -04:00
9900a56fa5
kcu105: initial checkin
2014-04-30 14:41:37 -04:00
Arpadi
Istvan Csomortani
Adrian Costina
AndreiGrozav
Rejeesh Kutty
Michael Hennerich
Lars-Peter Clausen