This reduces the amount of boilerplate code that is present in these
Makefiles by a lot.
It also makes it possible to update the Makefile rules in future without
having to re-generate all the Makefiles.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The project Makefiles for the Xilinx projects share most of their code. The
only difference is the list of project dependencies.
Create a file that has the common parts and can be included by the project
Makefiles.
This drastically reduces the size of the project Makefiles and also allows
to change the Makefile implementation without having to re-generate all
Makefiles.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The project Makefiles for the Altera projects share most of their code. The
only difference is the list of project dependencies.
Create a file that has the common parts and can be included by the project
Makefiles.
This drastically reduces the size of the project Makefiles and also allows
to change the Makefile implementation without having to re-generate all
Makefiles.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The TX side runs on QPLL, and the RX and RX_OS runs on CPLL by default.
The OUTCLK frequency is the same as the REFCLK.
The main reason of this modification is that the links should come up
without any DPR access, after power up, using the default reference clock
configuration (122.88 MHz).
This way the user do not need to modify the block design, just
set the required rate in system_bd.tcl.
This commit does not contain any functional changes.
Explicitly select MIO 52 and 53 pins to be part of MDIO port.
MIO_52_PIN (MDIO 0 Clock, Output)
MIO_53_PIN (MDIO 0 Data, Input/Output)
After the tool version change, this pins where by default connected
as MIO GPIOs.
Explicitly disable the "Transfer Start Synchronisation Support"
since the sync lines are not connected in this project.
If the sync input line (s_axi_user[0] or fifo_wr_sync) are not connected,
Vivado 2017.4.1 no longer connects them to the defaultValue defined
in the axi_dmac ip (1). Instead he uses the defaulValue field defined
in the interface definition which in case of both interfaces is 0;
Loop back the unused GPIO pins, and add all the SPI interface to system
wrapper instance.
The following system_top modules were changed:
- ad738x_fmc
- ad7616_sdz
- ad77681evb
- ad77681evb
- ad7768evb
- ad9739a_fmc
- ad9434
- adrv9739
- fmcadc5
- ad6676evb
- ad9265
- ad5766
- fmcomms5
- m2k
The constraint where added to remove timing problems on the reset path.
The constraint paths do not match anymore. The resets are used in a synchronous
way so we don't need the timing exceptions anyway.
Projects affected by this change:
- daq3
- adrv9739
- ad6676evb
- fmcadc5
- daq2/kcu105
- fmcadc2
- adrv9371x
- fmcomms11/zc706
- fmcjesdadc1
By default every base design has a SPI interface (hard or soft). In
case of soft IPs (xilinx), the input registers of the interface by default have
the IOB attribute set to TRUE. If the interface are not used, the tool will
generate a critical warning, stating that IOB registers are not connected to
an IO buffer.
The following constraints are disabling the above setup for every base
design, which using a soft SPI IP.
Set the properties to mirror the hardware configuration so
the Vivado tools can provide warnings if there are any conflicts
between configuration pin settings, such as an IOSTANDARD
on a multi-function configuration pin that conflicts with the
configuration voltage.
see:
https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf
The following base constraints were updated:
- kcu105
- kc705
- vc707
- ac701
To reduce compilation time use default stratagies for synthesis and
implementation. If a project will require custom strategies, enable it
just for that particular project.
This modification will affect both Intel and Xilinx projects.
Vivado sometimes generates semi-valid or invalid warnings and critical warnings.
In the past these messages were silenced, by changing its message severity.
These setups were scattered in multiple scripts. This commit is an attempt
to centralize it and make it more maintainable and easier to review it.
The script specifies the OUT_CLK_SEL and SYS_CLK_SEL parameter values as
binary numbers. But the tools will interpret them as decimal number
resulting in the wrong selection for OUT_CLK_SEL. Specify the parameter
values as decimal values to avoid this.
This is not a critical issue since software will overwrite this setting at
system boot-up. But it should be fixed anyway.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The script specifies the OUT_CLK_SEL and SYS_CLK_SEL parameter values as
binary numbers. But the tools will interpret them as decimal number
resulting in the wrong selection for OUT_CLK_SEL. Specify the parameter
values as decimal values to avoid this.
This is not a critical issue since software will overwrite this setting at
system boot-up. But it should be fixed anyway.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Fixes the following warning:
[Synth 8-2611] redeclaration of ansi port rx_sysref is not allowed
This is a leftover of commit 1c23cf4621 ("all: Update verilog files to
verilog-2001").
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Fixes the following warnings:
[Synth 8-2611] redeclaration of ansi port txnrx_0 is not allowed
[Synth 8-2611] redeclaration of ansi port enable_0 is not allowed
[Synth 8-2611] redeclaration of ansi port enable_1 is not allowed
[Synth 8-2611] redeclaration of ansi port txnrx_1 is not allowed
This is a leftover of commit 1c23cf4621 ("all: Update verilog files to
verilog-2001").
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Lars-Peter Clausen
Istvan Csomortani
AndreiGrozav
Rejeesh Kutty
Adrian Costina
Laszlo Nagy