4 Commits (36ef882da04ed1d0102297cc5f5f4fcd371ed766)

Author	SHA1	Message	Date
Istvan Csomortani	f9a67371c0	Zynq Base System: Reset is synchronized to lowest system clock ... System reset (sys_100m_reset) is synchronized to lowest system clock (FCLK0), via a Processor System Reset module	2014-03-26 17:58:14 +02:00
Rejeesh Kutty	dc44703cf1	zynq/non-zynq: identical signal names and instances	2014-03-17 17:02:03 -04:00
Rejeesh Kutty	f3ae57a53e	global clock and reset names	2014-03-11 09:57:59 -04:00
Rejeesh Kutty	ddac1a8834	added common board files	2014-02-28 21:17:01 -05:00