c44de7021a
axi_ad9739a: Fix DDS set frequency
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- DDS out frequency was 4 times greater than the desired frequency
2017-05-10 17:39:00 +03:00
5fe008d887
axi_ad9371: Update dac_clk_ratio to 2
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DAC sampling frequency is two times of the JESD204
core clock.
2017-05-10 11:12:45 +03:00
0e5a24ee7c
axi_fmcadc5_sync- raw inputs & constraint fixes
2017-05-08 10:30:51 -04:00
b6e9c92f46
axi_fmcadc5_sync- raw inputs & constraint fixes
2017-05-08 10:29:06 -04:00
391a14be7a
hdlmake.pl updates
2017-05-04 13:59:47 -04:00
1bd444b47f
axi_fmcadc5_sync- calcor added
2017-05-04 13:58:35 -04:00
f93a003ed1
axi_ad9434: Fix input data rate
2017-05-04 16:43:09 +03:00
6387b53266
ad77681evb: Initial commit
2017-05-04 12:19:11 +03:00
3ba57582bb
spi_engine_offload: Add a CDC module for trigger reception
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There are devices which have a asynchronous data ready signal. (asynchronous
with the spi clock) The CDC stages can be enabled by setting up
the ASYNC_TRIG parameter.
2017-05-04 12:14:06 +03:00
07956cfe66
spi_engine: Define parameter inside the module statement
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Part of the effort to update all verilog files to use the
ANSI-C style port list in module definitions. (verilog-2001)
2017-05-04 12:13:47 +03:00
ef97c1e375
adrv9371x/a10soc: Fix constraints
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Signed-off-by: Istvan Csomortani <istvan.csomortani@analog.com>
2017-05-02 14:37:11 +03:00
f0bc3e20ef
zcu102: Automatic IP version update fix
2017-05-02 12:52:43 +03:00
cd8f4f23be
zcu102: Automatic IP version update
2017-05-02 12:30:00 +03:00
d6b09602ed
usrpe31x: Automatic IP version update
2017-05-02 12:27:57 +03:00
485c810c2c
pzsdr*: Automatic IP version update
2017-05-02 11:43:32 +03:00
b3ce821311
change pl ddr clock to 1G
2017-05-01 09:35:10 -04:00
d29f420ffa
axi_fmcadc5_sync: add a calibration signal generation
2017-04-28 11:13:24 -04:00
7a53b99b8b
daq2: zc706: Increase DAC FIFO size
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Currently the DAC FIFO size for the ZC706 DAQ2 project is 16kB. This is
quite a limiting size for practical applications. Increase the size to 1MB
to allow loading larger waveforms.
In this configuration the DAC FIFO will use half of the available BRAM
cells in the FPGA. This still leaves quite a few BRAMs available for
user application logic added to the design. If a user design should run out
of BRAMs nevertheless they can reduce the FIFO size, if not required by the
application, to free up some cells.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-28 12:29:01 +02:00
f6eea23f5e
adaq7980: Update tcl command for IP configuration
2017-04-28 10:12:33 +03:00
353d1d44da
ad5766_sdz: Update tcl commands for IP configuration
2017-04-28 10:12:05 +03:00
956753ca9c
hdlmake- updates
2017-04-27 15:11:01 -04:00
68fc5c89a7
fmcadc5- remove stand alone psync
2017-04-27 15:09:56 -04:00
75c7525c60
fmcadc5- remove psync module
2017-04-27 13:29:06 -04:00
2027c8427c
adi_boadr- disconnect and remove unused ports
2017-04-27 13:26:17 -04:00
902eaaaf4c
fmcadc5- sync updates
2017-04-27 13:26:17 -04:00
0cb2316cb9
fmcadc5-sync- add ldo psync
2017-04-27 13:26:17 -04:00
0442e7d404
util_adxcvr: Fix parameter setup at instantiation
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If a parameter value is defined as a string binary (e.g. "001001000000"),
it can confuse the tool, and the value may be used as a decimal number.
To prevent this issue and to improve readability converting all the binary
constants into hexadecimal.
2017-04-27 15:35:39 +03:00
49ef9a589b
axi_ad5766: Fix parameter name for up_dac_common
2017-04-27 13:55:16 +03:00
8aa8d3a0e5
ad5766_sdz/zed: Fix i_iobuf_reset width
2017-04-27 11:28:26 +03:00
4e15a21b79
spi_engine_interconnect: Delete dependency defined for S1_CTRL interface
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The S1_CTRL interface is not dependent of the number of SDI lines.
2017-04-27 11:28:25 +03:00
4ceed4d373
util_pulse_gen: Add Makefile
2017-04-27 11:28:25 +03:00
4836aa2179
adaq7980/zed: Update Makefile
2017-04-27 11:28:25 +03:00
18a671cdb7
spi_engine: Expose DATA_WIDTH to software
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The value of DATA_WIDTH can be read back from register 0x44
The DATA_WIDTH will define the size of a word in a transaction.
2017-04-27 11:28:24 +03:00
801fb2281e
util_pulse_gen: The valid period is stored in pulse_period_d
2017-04-27 11:28:24 +03:00
fbccb377cc
adaq7980: Add an trigger generator for SPI offload
2017-04-27 11:28:23 +03:00
63cab50872
adaq7980_sdz: Initial commit
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The device is interfaced with a SPI Engine, the PD lines are controlled
by GPIOs.
2017-04-27 11:28:23 +03:00
a4c422ac4c
spi_engine_execution: Define port dependencies for SDI ports
2017-04-27 11:28:21 +03:00
045cb96744
axi_spi_engine: Define ports dependencies for up_* interface
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The up_* interface ports are active just if the MM_IF_TYPE is UP_FIFO.
2017-04-27 11:27:35 +03:00
ccc4aac505
ad5766_sdz: Fix the PIN assignment
2017-04-27 11:27:34 +03:00
8213d8a916
cn0363: Update block design
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Configure the interconnect and offload modules inorder to activate
its interfaces. In the past, these interfaces did not have any
parameter dependencies, so this configuration were not required.
2017-04-27 11:27:33 +03:00
9cd218eb90
up_dac_common: Increase datawidth of dac_datarate
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In case of high precision devices with just a simple SPI interface
for control and data, the effective data rate can be significatly
lower than the SPI clock, and more importantly there isn't any relation
between the two clock domain.
The rate is defined by a SOT (start of transfer) generator, which
initiates a SPI transfer. Taking the fact that the generator runs
on system clock (100 MHz), and the device can require smaller rate (in kHz domain),
the 7 bit dac_datarate register is just too small.
Therefor increasing to 16 bit.
2017-04-27 11:24:08 +03:00
a6146393be
ad5766_sdz: Fix DMA data path
2017-04-27 11:22:32 +03:00
a2c20551a2
axi_ad5766: Add Makefiles for the core
2017-04-27 11:22:31 +03:00
eba22892b8
axi_ad5766: Preserve consistent coding style
2017-04-27 11:21:15 +03:00
f5fba79a08
ad5766_zed: Add an IOBUF to the reset line
2017-04-27 11:21:14 +03:00
9de0fe56d9
ad5766: Integrate the new axi_ad5766 into the project
2017-04-27 11:21:14 +03:00
d061104a3c
util_pulse_gen: Add configuration interface for 'pulse period'.
2017-04-27 11:21:12 +03:00
825d46259b
interface: Update spi_engine_offload_ctrl definition
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Because of the new AD5766 offload module, SDO lines are
defined as 'optional'.
2017-04-27 11:19:22 +03:00
5c5baf3abf
spi_engine: Fix CMD_FIFO_VALID generation
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Because of the memory map interface mux, up_waddr_s should be used,
when cmd_fifo_in_valid is generated.
2017-04-27 11:19:20 +03:00
29f0ce36bb
axi_ad5766: Initial commit
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This core can be used in conjunction with the SPI_ENGINE, will work
as an offload module, forwarding a data stream to the SPI excecution,
received from a DMA.
2017-04-27 11:16:23 +03:00
AndreiGrozav
Istvan Csomortani
Rejeesh Kutty
Lars-Peter Clausen
Dragos Bogdan