ac2e5a9dac
constraints: Update constraints
...
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
e4e5b30ade
fmcadc5: Integrate ad_sysref_gen into the project
2017-01-03 13:52:39 +02:00
11b57290f1
fmcadc5- replaced with axi_adxcvr
2016-11-23 16:22:05 -05:00
cafc80c829
fmcadc5: add programmable io delay
2015-11-02 12:10:18 -05:00
08777ca566
fmcadc5- latest board changes
2015-10-15 10:46:07 -04:00
6dca97dd20
fmcadc5: 2014.4 updates
2015-03-23 10:00:46 -04:00
19e4950b72
renamed to match official names
2014-12-08 10:44:15 -05:00
Istvan Csomortani
Rejeesh Kutty