28159aeec9
a10soc- updates
2016-04-25 11:11:46 -04:00
0a3967b886
a10soc- updates
2016-04-25 10:53:26 -04:00
d36d1263c5
a10soc- updates
2016-04-25 10:50:09 -04:00
2a5f31d26b
fmcomms2/a10soc- copy
2016-04-22 15:15:44 -04:00
82c4f75f13
a10soc- a10gx copy
2016-04-22 10:39:21 -04:00
7a4a7edfba
daq2/a10gx: 10AX115S3F45E2SGE3 version
2016-04-20 16:07:41 -04:00
e00236e5fd
daq2/a10gx: 10AX115S3F45E2SGE3 version
2016-04-20 16:04:46 -04:00
8b2542b181
daq2/a10gx: 10AX115S3F45E2SGE3 version
2016-04-20 16:01:12 -04:00
679d471d75
Merge branch 'hdl_2016_r1' into dev
...
hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
402253d308
usb_fx3: Updated design to include the GPIF II interface
2016-04-19 15:52:30 +03:00
8a574cd8ba
zc706_system_plddr3.tcl : Add integration process for the AXI_DAC_FIFO
2016-04-19 11:30:52 +03:00
c291f8f107
daq1: Updated design to 2015.4
2016-04-14 23:36:47 +03:00
469b4ea5e8
fmcadc5: Updated design to 2015.4
2016-04-14 23:18:23 +03:00
62bd057106
fmcadc5/common: Update common design to 2015.4
2016-04-14 23:01:38 +03:00
a88ced8136
pzsdr1: lvds/cmos updates
2016-04-11 16:18:29 -04:00
3006c5a223
make updates
2016-04-11 16:14:59 -04:00
736bbdd95a
pzsdr1- io updates
2016-04-11 16:12:21 -04:00
8a5a5082f3
pzsdr1- io updates
2016-04-11 16:12:09 -04:00
8e689f4594
pzsdr1- lvds/cmos constraints
2016-04-11 16:00:18 -04:00
7e807d83b1
pzsdr1- cmos mode
2016-04-11 15:58:29 -04:00
bf6ef4e5f3
board- add disconnect
2016-04-11 15:33:00 -04:00
68bc647472
pzsdr1- ddr board delays update
2016-04-06 15:30:27 -04:00
21208ca208
Makefiles: Update Makefiles
2016-03-31 12:37:47 +03:00
1fab6ce477
daq2/common: Add util_dacfifo/dac_xfer_out control
2016-03-29 16:55:33 +03:00
255b0ebd40
util_dacfifo: Add dac_xfer_out control
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The dac_xfer_out control signal is asserted while the DAC reads back data. Should be connected to upack/dma_xfer_in.
2016-03-29 16:50:00 +03:00
657144d9a7
a10gx: Updated base design and DAQ2 to the new revision of the a10gx board
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- tried using ATX PLL and fPLL for TX transceiver clocks, but could not get them to lock
- CMU PLL works correctly as temporary solution
2016-03-28 13:21:36 +03:00
7c2f34549b
motcon2_fmc: Update common design to 2015.4
2016-03-23 10:27:07 +02:00
373481360b
util_dacfifo: Add a bypass option to the FIFO
2016-03-21 14:14:43 +02:00
714caa964c
usdrx1: Update common design to 2015.4
2016-03-18 16:29:43 +02:00
05f4f3ac09
usb_fx3: Update common design to 2015.4
2016-03-18 16:16:38 +02:00
24fdd2b9b7
pzsdr/ccpci: Update common design to 2015.4
2016-03-18 15:30:10 +02:00
f8b155faab
pzsdr/ccfmc: Update common design to 2015.4
2016-03-18 15:28:56 +02:00
d567af54ef
imageon: Update common design to 2015.4
2016-03-18 15:27:31 +02:00
995debedce
fmcomms2: Update common design to 2015.4
2016-03-18 15:26:52 +02:00
b555be25d5
kcu105: Update common design to 2015.4
2016-03-18 15:22:42 +02:00
412013d939
adv7511: Update common design to 2015.4
2016-03-18 15:01:25 +02:00
d355aa0ea6
daq3/zc706: Updated design to 2015.4
2016-03-17 11:46:48 +02:00
012b095006
daq3: Updated common design to 2015.4
2016-03-17 11:44:27 +02:00
38c3f7474a
ad6676: Updated common design to 2015.4
2016-03-17 11:40:46 +02:00
abc03fff2c
fmcomms7: Updated design to 2015.4
2016-03-17 09:11:41 +02:00
59c726ecbe
fmcjesdadc1: Updated common design to 2015.4
2016-03-16 10:14:06 +02:00
1a3aab0c13
fmcomms1: Updated common design to 2015.4
2016-03-16 10:09:54 +02:00
b7be089b82
daq2: Updated common design to 2015.4
2016-03-16 10:02:42 +02:00
697469ee28
daq1- updates
2016-03-15 12:39:38 -04:00
334fce03a3
fmcadc4/zc706: Updated design to 2015.4
2016-03-15 15:28:11 +02:00
e8dd5f9788
fmcadc4: Updated common design to 2015.4
2016-03-15 15:27:25 +02:00
98cc7dad7d
fmcadc2: Updated common design to 2015.4
2016-03-15 15:26:05 +02:00
ceea7f25b2
fmcomms2: Updated common design to 2015.4
2016-03-15 15:23:20 +02:00
6f03998b95
zc702: Updated common design to 2015.4
2016-03-15 15:21:22 +02:00
a0c5f46940
zed: Updated common design to 2015.4
2016-03-15 15:20:46 +02:00
9a258d5e4c
vc707: Updated common design to 2015.4
2016-03-15 15:20:02 +02:00
bcf5bd8137
mitx045: Updated common design to 2015.4
2016-03-15 15:18:31 +02:00
27f5f1dcbe
kc705: Updated common design to 2015.4
2016-03-15 15:17:53 +02:00
eb743e0e03
ac701: Updated common design to 2015.4
2016-03-15 15:17:02 +02:00
d282064103
zc706: Updated common design to 2015.4
2016-03-15 15:16:36 +02:00
71be9519ec
adi_project.tcl: Updated to 2015.4
2016-03-15 15:03:50 +02:00
33b265a742
Makefile: Update Makefiles
2016-03-14 09:31:17 +02:00
561412e322
pzsdr-cmos swap
2016-03-11 11:25:58 -05:00
c7ee15d4f4
ccbrk_cmos: cmos mode
2016-03-11 11:25:58 -05:00
c566784ba9
ccbrk_cmos: ccbrk copy
2016-03-11 11:25:58 -05:00
b0f90bd0e8
daq1/cpld: Read interface fix
2016-03-04 20:28:24 +02:00
7e607957ee
daq1.cpld: Prevent the spi_counter to roll over.
2016-03-04 20:28:22 +02:00
262a42c676
daq1/cpld: Update CPLD_VERSION value
2016-03-04 20:28:20 +02:00
9439862301
daq1/cpld: Update CPLD
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Change to control line fpga_to_cpld to cpld_to_fpga, this is not a functional change.
2016-03-04 20:28:18 +02:00
3466f21f8e
pzsdr add cmos/lvds support
2016-03-04 10:39:48 -05:00
18f30c8dc8
pzsdr- cmos/lvds split
2016-03-04 10:39:48 -05:00
a2374f64bf
pzsdr- cmos/lvds split
2016-03-04 10:39:48 -05:00
977d9d0624
Merge branch 'hdl_2015_r2' into dev
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Conflicts:
projects/daq1/common/daq1_spi.v
2016-03-02 13:52:15 +02:00
40fb68dfd5
ad9265, ad9434, ad9467, daq1, daq2, daq3, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1, fmcomms6, fmcomms7, usdrx1: updated common spi module so that spi streaming is possible
2016-03-02 13:39:37 +02:00
becc23a69b
daq2: Modified common spi module so that spi streaming is possible
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- stop incrementing spi_count after the instruction cycle
2016-03-01 17:25:58 +02:00
f7e490c2b3
hdlmake.pl updates
2016-02-26 13:46:11 -05:00
e012d0519b
Merge remote-tracking branch 'origin/hdl_2015_r2' into dev
2016-02-26 13:39:39 -05:00
f6e64e42b0
kcu105: add ethernet idelaycntrl
2016-02-26 13:19:49 -05:00
59313f3c90
daq1: ADC DMA must be in none-cyclic mode
2016-02-24 14:37:19 +02:00
c0a559a9b1
daq1: Fix some typos in the SPI wrapper
2016-02-24 14:31:56 +02:00
8ccd8d87bb
daq2: A10GX, increase analog/digital reset durations
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- reset the xcvr_rst_cntrl only from the axi_jesd_xcvr
- checked separate RX/TX reset per channel
2016-02-23 11:41:38 +02:00
89f7aadfb1
fmcjesdadc1: A5GT, connected xcvr_rxt_cntrl reset input to the axi_jesd_xcvr reset output
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This will allow for the transceivers to be reset by the axi_jesd_xcvr core
2016-02-23 11:31:07 +02:00
4fb6589b2d
pzsdr/ccfmc: add fan controls
2016-02-19 16:40:54 -05:00
377461e0d4
Merge branch 'hdl_2015_r2' into dev
2016-02-19 14:15:27 +02:00
0f37dd6424
fmcjesdadc1: Fixed project
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- changed system_project.tcl so that all base designs to be included
- changed DMA properties to take into consideration the new parameter names
- changed reset bridges to asynchronous
- increased maximum burst size of the DMA bridge
- changed the data_width of the memory bus to 256, as with 512 timing violations may occur
- changed base addresses for the base system to be the same as in the previous release
2016-02-19 14:09:57 +02:00
ce760eb691
fmcadc2- add adf4355 access
2016-02-18 16:17:33 -05:00
d94f157454
arradio: Changed ADC/DAC DMA address length to 24 bit
2016-02-16 15:27:51 +02:00
43e03ca6f7
arradio: Updated project
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- made the reset bridges asynchronous
- connected the arradio gpio to the CPU interconnect
2016-02-16 14:50:23 +02:00
5518c47ca4
daq1_cpld: Set Input and tristate I/O termination mode to FLOAT
2016-02-15 19:27:59 +02:00
051ac307e6
daq1_cpld: Do not forward the first eight clock cycles of fmc_spi_sclk to sclk
2016-02-15 19:26:58 +02:00
9370246cfa
daq1: Fix bugs on CPLD design
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Fix the CSN forwarding.
2016-02-12 16:59:09 +02:00
5ed2c0b599
daq1: Update CPLD constraints file
2016-02-12 16:54:36 +02:00
aa2ff0223a
daq1: Update CPLD design
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+ SPI counter counts on negative edge of the SPI_CLK
+ Shift register for read, shifting MSB first
+ Fix write access logic
+ Update the internal register addresses
2016-02-12 14:45:18 +02:00
c32d7147d5
daq1 : There is a single CSN from master
2016-02-12 14:38:32 +02:00
9675df15c6
daq1_zc706: Update constraints file
2016-02-12 14:37:02 +02:00
e381d5170c
util_tdd_sync: Update the synchronization interface
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Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-12 14:27:37 +02:00
61f9f72a75
fmcjesdadc1: Updated VC707 project for maximum throughput from DMA to DDR
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- Increased the DMAs internal FIFO
2016-02-09 12:30:56 +02:00
c431adb793
fmcjesdadc1: Updated KC705 project for maximum throughput from DMA to DDR
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- Increased the DMA internal FIFO
2016-02-09 12:00:27 +02:00
ad9ecbbbb6
daq2: Updated a10gx project to quartus 15.1.1
2016-02-05 17:43:05 +02:00
bb62f6d225
pzsdr1- updates
2016-02-02 12:34:09 -05:00
41b6ebeeaf
pzsdr1- updates
2016-02-02 12:33:55 -05:00
b147e9c94a
pzsdr1- updates
2016-02-02 12:33:01 -05:00
170295161f
pzsdr1- xdc
2016-01-26 11:19:00 -05:00
bcac3eef4d
pzsdr1- initial commit
2016-01-25 16:07:33 -05:00
44a382fc69
pzsdr1-added
2016-01-25 15:33:34 -05:00
Rejeesh Kutty
AndreiGrozav
Adrian Costina
Istvan Csomortani