341221dc91
jesd204: Update jesd204_tx_lane.v
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Removed decoder for tx_ready.
2020-04-01 10:29:40 +03:00
4e191e7ac2
ad_ip_jesd204_tpl_dac: fix GUI and FPGA info population
2020-03-10 18:33:29 +02:00
557a72e35e
ad_ip_jesd204_tpl_adc: fix GUI and FPGA info population
2020-03-10 18:33:29 +02:00
1b0a47c101
jesd204_rx: fix critical warning for undriven input
2020-03-10 18:17:56 +02:00
9cce513645
jesd204/axi_jesd204_tx: Update version
2020-02-10 09:47:07 +02:00
b8e1daa22b
jesd204/axi_jesd204_rx: Update version
2020-02-10 09:47:07 +02:00
587a3c1a8d
scripts/jesd204.tcl: Added 64b mode to Rx scripting
2020-02-10 09:47:07 +02:00
72186324f3
tb/loopback_64b_tb: Testbench for 64b mode
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Data integrity check over a loopbacked link.
2020-02-10 09:47:07 +02:00
bd9836886f
jesd204_rx_static_config: Added 64b mode to Rx static config
2020-02-10 09:47:07 +02:00
c3afbbc8a8
jesd204/interfaces: Added 64b mode Rx signals
2020-02-10 09:47:07 +02:00
7cad1f81d9
axi_jesd204_rx: Added 64b mode
2020-02-10 09:47:07 +02:00
d1072847df
jesd204_rx: 64b mode support for receive peripheral
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Instantiate 64B/66B decoder based on synthesis parameter.
2020-02-10 09:47:07 +02:00
075f703443
jesd204_tx_static_config: Added 64b mode Tx static config
2020-02-10 09:47:07 +02:00
e2d12a5b53
jesd204/scripts: Add 64b mode to Tx scripting
2020-02-10 09:47:07 +02:00
c574861bf4
axi_jesd204_tx: Add 64b mode for control interface
2020-02-10 09:47:07 +02:00
d9a31e8d83
jesd204_tx: Support for 64b mode in transmit peripheral
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Instantiate 64B/66B mode encoder based on synthesis parameter.
2020-02-10 09:47:07 +02:00
b40e055ebe
jesd204/jesd204_common/jesd204_lmfc: Add multiblock clock edge, EoEMB
2020-02-10 09:47:07 +02:00
72e9a563da
jesd204_common: Added JESD204C components
2020-02-10 09:47:07 +02:00
20ae7a8f7d
jesd204: CRC12 component
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The component can be used in Tx to compute CRC on the data to be send as
in the Rx side to compute CRC on the received data.
2020-02-10 09:47:07 +02:00
a5346412d1
jesd204: Scrambler for 64b mode
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The component can be used for scrambling in Tx and descrambling on the
Rx side of the JESD link.
2020-02-10 09:47:07 +02:00
474e07e579
jesd204: Add parameter for TPL data width
2020-02-10 09:47:07 +02:00
f2060e27be
jesd204_tx: add output pipeline stage
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In order to help timing closure on multi SLR FPGAs add a pipeline stage
between the link layer and physical layer. This will add a fixed amount
of delay to the overall latency.
2020-02-07 09:02:46 +02:00
7612b5d8dd
scripts/jesd204.tcl: add support for more lanes and converters for TPLs
2019-11-28 16:17:21 +02:00
85eabc5a08
jesd204/ad_ip_jesd204_tpl_dac: add support for more lanes and converters
2019-11-28 16:17:21 +02:00
002f8d8a3e
jesd204/ad_ip_jesd204_tpl_adc: add support for more lanes and converters
2019-11-28 16:17:21 +02:00
db573a59b0
jesd204: support for 16 lanes
2019-11-28 16:17:21 +02:00
acba490c2e
ad_ip_jesd204_tpl_adc: BITS_PER_SAMPLE is a HDL parameter
2019-10-02 15:32:17 +03:00
aa5fdf903e
Makefile: Update makefiles
2019-08-26 16:58:01 +03:00
fe09acaa2f
up_axi_update: ADDRESS_WIDTH parameter is now a localparam
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ADDRESS_WIDTH is now AXI_ADDRESS_WIDTH - 2;
up_axi instantiations will set AXI_ADDRESS_WIDTH instead of ADDRESS_WIDTH;
2019-07-26 11:58:58 +03:00
0f7a3b953a
scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface
2019-06-29 06:53:51 +03:00
04ce10a570
cosmetics: Change Altera to Intel in comments
2019-06-29 06:53:51 +03:00
5329458a62
library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl
2019-06-29 06:53:51 +03:00
363494ab9c
library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl
2019-06-29 06:53:51 +03:00
79b6ba29ce
all: Rename altera to intel
2019-06-29 06:53:51 +03:00
65fea6c4c0
ad_ip_jesd204_tpl_dac: Fix up_axi instantiation
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This patch will fix the following warning:
[Synth 8-689] width (16) of port connection 'up_axi_awaddr'
does not match port width (12) of module 'up_axi'
2019-06-27 13:47:00 +03:00
9832c87144
jesd204:tpl: add missing dependencies for Intel
2019-05-24 11:04:46 +03:00
157afcbc33
tb_base: Fix various test benches
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The tb_base.v verilog files does not contain a full module definition,
just some plain test code. In general the files is sourced inside the
test bench main module. As is, defining a timescale in these files will
generate an error, because timescale directive can not be inside a
module.
Delete all the timescale directive from these files.
2019-05-17 11:20:48 +03:00
b90c2e79dc
jesd204_rx: add parameter for input pipeline stages
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Pipeline stages must be implemented on register so placer can spread it
cross the device. Use the shreg_extract attribute to avoid SRL
inference.
2019-05-16 13:29:34 +03:00
92d87c2d60
jesd204/scripts: fix indentation
2019-05-16 13:22:55 +03:00
cf258ace83
jesd204/scripts: TPL add support for M=1
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When only one converter is used there is no need for concatenation and
slicer cores. In that case the TPL will connect to port 0 from the
application layer.
2019-05-16 13:22:55 +03:00
168e1951ee
library: Add `timescale to modules that are missing it
2019-05-15 15:37:44 +03:00
c32b4b02f3
sync_bits: Change I/O names of wires "in" and "out" for VHDL users
2019-04-23 18:03:23 +03:00
01748d4364
jesd204:axi_jesd204_tx: set OOC default clock constraints
2019-04-22 10:27:16 +03:00
4264a7a0dd
jesd204:axi_jesd204_rx: set OOC default clock constraints
2019-04-22 10:27:16 +03:00
66823682b6
Add FPGA info parameters flow
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Common basic steps:
- Include/create infrastructure:
* Intel:
- require quartus::device package
- set_module_property VALIDATION_CALLBACK info_param_validate
* Xilinx
- add bd.tcl, containing init{} procedure. The init procedure will be
called when the IP will be instantiated into the block design.
- add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl
- create GUI files
- add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params)
- add/propagate the info parameters through the IP verilog files
axi_clkgen
util_adxcvr
ad_ip_jesd204_tpl_adc
ad_ip_jesd204_tpl_dac
axi_ad5766
axi_ad6676
axi_ad9122
axi_ad9144
axi_ad9152
axi_ad9162
axi_ad9250
axi_ad9265
axi_ad9680
axi_ad9361
axi_ad9371
axi_adrv9009
axi_ad9739a
axi_ad9434
axi_ad9467
axi_ad9684
axi_ad9963
axi_ad9625
axi_ad9671
axi_hdmi_tx
axi_fmcadc5_sync
2019-03-30 11:26:11 +02:00
8340d4c89d
axi_jesd204_common: Fix dependancies so that the IP can be generated Out Of Context
2019-03-21 15:36:57 +02:00
a337774dfa
ad_ip_jesd204_tpl_dac: Add 8 bit resolution support
2019-03-20 15:51:28 +02:00
e3e96177c4
ad_ip_jesd204_tpl_adc: Add 8 bit resolution support
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Add support for 8 bit resolution for the transport layer.
Fix parameter BITS_PER_SAMPLES propagation to all the internal modules, in
several cases this variable was hard coded to 16.
2019-03-20 15:51:28 +02:00
b221718bfe
jesd204:up_tpl_common: reduce and move address space
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Limit the tpl register space to 128 locations mapped to 128-255 in the COMMON_ID segment.
2019-01-23 17:44:33 +02:00
cf593d5a40
jesd204_tpl: addresses cleanup
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The TPL has an address space of 12 bits while the legacy subcomponents
have 16 bits. Update the module for a better readability.
2019-01-23 17:44:33 +02:00
Maxim
Laszlo Nagy
Istvan Csomortani
Arpadi
Adrian Costina
AndreiGrozav