c88cbf78af
fmcomms5: Added wfifo at the between AD9361 and cpack core
2015-11-13 15:50:32 +02:00
bec4c8da84
pzsdr: Update Make files
2015-11-11 11:16:05 +02:00
2345d29663
fmcomms2: Update make files
2015-11-11 11:15:45 +02:00
a936ad607f
fmcomms2/zc706: Delete unused files from file list
2015-11-11 11:14:58 +02:00
c7e86528d6
fmcomms2/zc706: Cosmetic changes on constraints file
2015-11-11 11:14:16 +02:00
6197a82c80
fmcomms2/common: Add the util_tdd_sync module
2015-11-11 11:07:15 +02:00
5cc97c78d3
Makefiles: Update makefiles to include the nerw axi_gpreg / util_mfifo libraries
2015-11-10 09:32:50 +02:00
ef9bdf6ec9
adi_project: Regenerate the layout of the IP Integrator subsystem design.
2015-11-09 11:01:10 +02:00
1d6254fdec
pzsdr/ccbrk: loopback board support
2015-11-06 11:34:21 -05:00
afc4274ee3
common scripts: Changed the resulting hdf file to system_top_bad_timing, if design doesn't meet timing.
2015-11-06 16:01:19 +02:00
0c7c0f2cd8
common scripts: Change the name of the generated HDF if the design doesn't meet timing
2015-11-05 18:41:51 +02:00
11718291cf
pzsdr/ccfmc- add single loopback core
2015-11-05 11:28:38 -05:00
9e27a60478
pzsdr/ccfmc- single loopback core
2015-11-05 11:28:33 -05:00
e36f27b061
daq2: Update A10GX project, with the latest changes.
...
Works with up to 64k samples
2015-11-04 14:54:09 +02:00
83399ef6ee
a10gx: Updated common project to work with Linux (enabled MMU)
2015-11-04 13:35:52 +02:00
a0039ed4fe
ccfmc: Launch HDMI data on falling edge
...
The ADV7511 captures data on the rising edge, so make sure to launch data
on the falling edge. This fixes some issues with image stability.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-11-03 10:59:13 +01:00
6dddac5d94
ccfmc- missing board io
2015-11-02 15:45:14 -05:00
cafc80c829
fmcadc5: add programmable io delay
2015-11-02 12:10:18 -05:00
8b95520767
pzsdr/ccfmc- add loopback gpio/gt cores
2015-10-30 18:48:26 -04:00
92b7570864
pzsdr/ccfmc- add ad9517 signals
2015-10-30 10:50:53 -04:00
b3cb84cf91
fmcadc5- added ila
2015-10-29 16:48:21 -04:00
24d76c610a
fmcadc5- fix core connections
2015-10-29 16:47:56 -04:00
ac4091e19e
fmcadc4- add monitor fifo
2015-10-27 14:52:02 -04:00
b5d3d0bd13
usb_fx3: Added axi_usb_fx3 core and DMA to the project
2015-10-27 09:41:18 +02:00
748a2bc87a
fmcadc4- add ila for zc706 only
2015-10-23 14:32:35 -04:00
b2d0f5c56e
fmcadc4- use the same source/name for clocks
2015-10-23 14:32:35 -04:00
9d2b8809df
Makefiles: Updated Makefiles
2015-10-23 10:44:27 +03:00
cb2bda48c0
fmcadc5- gt/ip updates
2015-10-19 09:31:32 -04:00
ed918ec119
imageon - keeping scripts happy
2015-10-16 15:04:02 -04:00
e14e9294c5
project-names -- variables causes scripts to fail- too much parsing
2015-10-16 14:13:56 -04:00
36dd6427fe
pzsdr: Add untracked Makefiles
2015-10-16 13:58:36 +03:00
bbdc693954
pzsdr/all: Update Makefile
2015-10-16 11:57:51 +03:00
08777ca566
fmcadc5- latest board changes
2015-10-15 10:46:07 -04:00
030485de28
fmcadc5- regulators need a switching ref clock?
2015-10-15 10:46:07 -04:00
f966f79e5f
fmcadc5- regulators need a switching ref clock?
2015-10-15 10:46:07 -04:00
199227b78c
fix fmcjesdadc1_bd ILA warning
2015-10-13 10:19:08 -04:00
21737ad7b8
fmcomms2/zc706pr: Update the fifo interface of the PR module
2015-10-13 11:37:44 +03:00
c9a5057b93
library/prcfg : Split data bus to channels
...
Because of the new pack/upack modules on the data path, it makes more sense to split the data interface of the PR modules into separate channels.
The top module will supports max 4 channels.
2015-10-13 11:36:45 +03:00
9bb70e2b69
motcon2_fmc: Updated ZED project
2015-10-09 15:33:31 +03:00
83fb5c742a
motcon2_fmc: Updated project to Vivado 2015.2.1
...
- added cpack cores
- removed controller DMA paths
2015-10-09 13:56:41 +03:00
88e8bef92f
usdrx1: Update ZC706 project
2015-10-09 13:33:45 +03:00
02c0a5f5df
usdrx1: Update project to Vivado 2015.2.1
2015-10-09 13:33:07 +03:00
c83239b014
fmcomms2/zc706pr: Update PR design
...
+ Add system_top.v to design
+ Add pr specific constraints
2015-10-09 13:23:42 +03:00
09be227db9
fmcomms2/zc706pr: Update PR design
...
+ Add system_top.v to design
+ Add pr specific constraints
2015-10-09 13:19:09 +03:00
e4517c0d6a
daq2/common: Connect reset to dac fifo
2015-10-08 16:51:08 +03:00
df88b33946
usb_fx3: Initial commit
...
Only the UART connections are available.
The FMC should not be populated at this time
2015-10-02 09:30:31 +03:00
b93af3c21e
daq3- bd updates
2015-09-30 10:11:49 -04:00
81a1c21553
util_pmod_adc: Reset line changed to active low reset.
2015-09-30 12:33:46 +03:00
5f12c8c7d4
cftl_cip/common: Fix parameter names for dmac
2015-09-30 12:32:48 +03:00
3dc881dbb3
pmods/xfest14: Delete directory
...
This project will not be supported from the next release
2015-09-30 12:25:31 +03:00
e6af671bea
cn0363/zed: Fix DMAC parameter names
2015-09-30 11:31:53 +03:00
4aa4ffc25f
imageon/common: Update cores to Vivado 2015.2
2015-09-29 18:51:46 +03:00
e60d2f86b3
imageon/common: Fix parameter name for spdif_rx
2015-09-29 18:50:41 +03:00
b4252a8512
imageon_loopback: Delete directory
...
This project will not be supported from the next releases.
2015-09-29 14:53:44 +03:00
9832cea071
ad9739a_fmc: Common, reduced DMA fifo size
2015-09-28 12:19:23 +03:00
5b48340b08
fmcomms6: Updated ZC706 project
2015-09-28 11:32:20 +03:00
3b3c645827
fmcomms6: Updated project to Vivado 2015.2.1. Added cpack
2015-09-28 11:31:08 +03:00
046c89dacd
fmcomms2/pr: Delete the fmcomms2_pr directory
...
The fmcomms2/pr project is moved to fmcomms2/zc706pr
2015-09-25 19:11:43 +03:00
f77f928444
fmcomms2/zed: Fix the system_top
...
Fix the enable/txnrx control line.
2015-09-25 19:11:41 +03:00
aeb1d7aa3e
fmcomms2/zed: Cosmetic changes
2015-09-25 19:11:39 +03:00
f8b3096bd0
fmcomms2/vc707: Fix the system_top
...
Fix the enable/txnrx control lines.
2015-09-25 19:11:37 +03:00
2c75cfd04e
fmcomms2/vc707: Cosmetic changes
2015-09-25 19:11:35 +03:00
ffa0bcd19f
fmcomms2/mitx045: Fix the system_top
...
Fix the enable/txnrx control lines.
2015-09-25 19:11:32 +03:00
28d20e84c5
fmcomms2/zc702: Fix the system_top
...
Fix the enable/txnrx control lines.
2015-09-25 19:11:30 +03:00
ea74413125
fmcomms2/kc705: Fix the system_top.
...
Fix the enable/txnrx control lines.
2015-09-25 19:11:28 +03:00
f80622b972
fmcomms2/ac701: Fix the system_top
...
Fix the enable/txnrx control line.
2015-09-25 19:11:26 +03:00
07e2d281c0
Make: Update Make files
2015-09-25 19:11:21 +03:00
1604e88242
fmcadc4: Update project to the new JESD interface framework
2015-09-25 19:11:19 +03:00
f4b432da08
fmcadc4: Update to 2015.2
2015-09-25 19:11:17 +03:00
4f99bdd93f
fmcadc5: Update project
...
+ Update the JESD IP core for Vivado 2015.2
+ Update the framework for JESD interface
2015-09-25 19:11:14 +03:00
f5b5bbfbca
fmcomms7: Update to the new JESD framework
...
Update project to the new framework for JESD interface and add a DAC FIFO to the transmit path.
2015-09-25 19:11:12 +03:00
fbd51c2734
fmcomms7: Update to 2015.2
...
Update IP core version of jesd204.
2015-09-25 19:11:10 +03:00
d198caa621
fmcomms2: Updated ZC702 design
2015-09-25 18:15:40 +03:00
4b115fbe69
ad9467_fmc: Delete ILA from the design
2015-09-25 17:41:46 +03:00
7853843036
fmcomms5: Update ZC706 project
2015-09-25 17:32:29 +03:00
108ffebae4
fmcomms5: Updated project to 2015.2.1
...
- added cpack / upack
2015-09-25 17:31:08 +03:00
848b51699c
fmcadc2: Updated VC707 project
2015-09-25 17:28:15 +03:00
e764f54426
fmcadc2: Updated ZC706 project
2015-09-25 17:26:54 +03:00
6fbd8dd9a5
fmcadc2: Update projecct to 2015.2.1
...
- updated to the new jesd framework
2015-09-25 17:25:32 +03:00
ab4b73fd32
ad6676evb: Updated VC707 project
2015-09-25 16:07:22 +03:00
33390c85f8
ad6676evb: Update ZC706 project
2015-09-25 14:46:02 +03:00
a49230ec07
ad6676evb: Updated project to 2015.2.1
...
- updated to the new jesd framework
- added cpack core
2015-09-25 14:44:46 +03:00
7f9c526683
fmcjesdadc1: VC707 update project
2015-09-24 19:50:14 +03:00
78fe05120b
fmcjesdadc1: Updated KC705 project
2015-09-24 19:14:48 +03:00
70c7c2aeb8
fmcjesdadc1: Updated ZC706 project
2015-09-24 19:14:05 +03:00
2ed161628d
fmcjesdadc1: Updated project to 2015.2.1
...
- updated to the new jesd framework
- added cpack core
2015-09-24 19:12:40 +03:00
58ab70bc0e
fmcomms1: Update AC701 project
...
Renamed mdio pin, as it's exported by the system wrapper
Renamed DMA parameter
2015-09-24 19:07:19 +03:00
f9801e8c85
pzsdr/cc*- rf card on fmc only
2015-09-23 09:16:41 -04:00
9832ea95a8
pzsdr/ccpci- initial version
2015-09-22 16:30:27 -04:00
14bccb6062
pzsdr/ccfmc- rf card/tdd only on fmc
2015-09-22 15:54:53 -04:00
fa5d879fdb
pzsdr/ccpci -- updates
2015-09-21 14:54:31 -04:00
fce96099ab
unused eth1 clocks
2015-09-21 14:54:31 -04:00
0702f2c231
ccpci- added
2015-09-21 09:31:18 -04:00
3a72d26f5b
pzsdr- pci carrier
2015-09-18 21:18:16 -04:00
9f8433159f
pzsdr- name changes
2015-09-18 16:24:27 -04:00
0d232a270a
pzsdr- breakout + fmc updates
2015-09-18 15:34:56 -04:00
3bd2bc4071
pzsdr- breakout + fmc updates
2015-09-18 15:34:36 -04:00
25f3f05c22
pzsdr- breakout + fmc updates
2015-09-18 15:33:50 -04:00
93b928033b
ccbrk- added
2015-09-18 13:24:26 -04:00
caec400378
pzsdr- make module default
2015-09-18 13:22:01 -04:00
236854c26f
pzsdr-cc-fmc updates
2015-09-18 12:46:42 -04:00
f970bf1786
pzsdr fmc carrier
2015-09-18 11:50:08 -04:00
b3a4f11e97
rfsom to pzsdr
2015-09-18 11:48:30 -04:00
0386bedff9
fmc carrier is -- ccfmc
2015-09-18 11:45:56 -04:00
92533bc24d
fmc carrier is -- ccfmc
2015-09-18 11:45:15 -04:00
48af5f29de
rfsom renamed to pzsdr
2015-09-18 11:19:50 -04:00
3ef94d559c
rfsom renamed to pzsdr
2015-09-18 11:18:59 -04:00
52d3f189a0
rfsom renamed to pzsdr
2015-09-18 11:18:01 -04:00
e2886eaa44
pzpcie- updates
2015-09-18 11:10:48 -04:00
379f788c8c
pzpcie- added
2015-09-18 11:10:48 -04:00
9e68357af5
usdrx1: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:19 +02:00
275830d2b1
motcon2_fmc: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:17 +02:00
8d179235f8
imageon: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:14 +02:00
9210e1d58a
fmcomms7: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:11 +02:00
39b032b868
fmcomms5: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:09 +02:00
cd8b467b1e
fmcomms2: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:07 +02:00
7e2255f4d9
fmcjesdadc1: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:05 +02:00
dd79dfdc12
fmcadc5: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:03 +02:00
7f5a22a75f
fmcadc4: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:01 +02:00
60490c4e2b
fmcadc2: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:59 +02:00
6c7316fbd0
daq3: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:56 +02:00
7184827d68
daq2: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:54 +02:00
f1fb599eb1
cn0363: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:51 +02:00
6d87f537da
cftl_cip: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:49 +02:00
1c603b830e
ad9467_fmc: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:47 +02:00
960c711f3b
ad9434_fmc: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:44 +02:00
7be1f62b8b
ad9265_fmc: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:25 +02:00
0f553a08e8
ad6676evb: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:21 +02:00
0021c7869d
kc705: Deactivated narrow burst support, as it's not needed
2015-09-16 19:02:17 +03:00
70cea5b14e
fmcomms1: Removed ILA
2015-09-16 18:51:40 +03:00
63aaa58861
ad9265_fmc: Updated project, removed ILA related clocks
2015-09-11 11:27:58 +03:00
a679251d7d
Makefiles: Update Make
2015-09-09 17:13:19 +03:00
f3eca48533
pzsdr_rfsom: Update project with the new TDD sync interface
2015-09-09 12:37:52 +03:00
510f1cfdd9
fmcomms2_zc706: Update project with the new TDD sync interface
2015-09-09 12:35:22 +03:00
f428d8bde9
adv7511: KC705, updated design so that the axi_hdmi_dma core has memory connection datawidth of 512
2015-09-08 16:43:40 +03:00
d81d8238a9
kc705: Updated mig project file
2015-09-08 16:42:23 +03:00
2757cd8baf
adv7511: AC701 fixed system top
2015-09-07 16:48:10 +03:00
214f5b18c1
no-trace option
2015-09-03 16:16:31 -04:00
00a55ded00
ibert to jesd-gt change
2015-09-03 16:16:30 -04:00
77ee3c4cbc
ibert to jesd-gt change
2015-09-03 16:16:28 -04:00
dbf7c154b2
no-trace option
2015-09-03 16:16:27 -04:00
e2aca435e5
ibert-to-jesd-gt change
2015-09-03 16:16:25 -04:00
f1d416a98b
daq2/a10gx- ethernet fix
2015-09-02 14:31:15 -04:00
1fff1076b1
daq2/a10gx- ethernet fix
2015-09-02 14:31:15 -04:00
01c0fdc809
daq2/a10gx- ethernet fix
2015-09-02 14:31:15 -04:00
1ecd615f92
common/mitx045 : Fix the vdma interface of axi_hdmi_core
2015-09-02 16:33:30 +03:00
9fb336e464
usdrx1: Add DDR FIFO
...
The converters on the usdrx1 generate 2.5GB/s. This more than we can
transport over the HP interconnects to the system memory.
Add a dedicated DDR FIFO to design which can be used to buffer the data
before it is transferred to the main memory.
Also increase the interconnect clock rate from 100MHz to 200MHz and the DMA
FIFO size from 4 to 8, so we can transfer the captured data faster to the
main memory.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
bbada6ed8f
usdrx1: Add overflow flag to ILA
...
It's useful to know if and when a overflow happens.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
c67aecc1eb
usdrx1: Disable SYNC_TRANSFER_START for the DMA
...
There is no sync signal in this design, so the flag needs to be set to 0.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
c00a6af4db
usdrx1: Add DDR FIFO
...
The converters on the usdrx1 generate 2.5GB/s. This more than we can
transport over the HP interconnects to the system memory.
Add a dedicated DDR FIFO to design which can be used to buffer the data
before it is transferred to the main memory.
Also increase the interconnect clock rate from 100MHz to 200MHz and the DMA
FIFO size from 4 to 8, so we can transfer the captured data faster to the
main memory.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:21:45 +02:00
Adrian Costina
Istvan Csomortani
Rejeesh Kutty
Lars-Peter Clausen
Nicholas Pillitteri