zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
2,718 Commits
1 Branch
0 Tags
23 MiB
Commit Graph

6 Commits (3351ff607e55574f30c90942398fa17d83ddfd54)

Author SHA1 Message Date
Istvan Csomortani e1495b89f9 axi_dacfifo: Cosmetic changes 2016-05-27 14:13:55 +03:00
Istvan Csomortani c724c027c4 axi_dacfifo: Fix the synchronizers 2016-05-27 14:13:55 +03:00
Istvan Csomortani 183c67aca0 axi_dacfifo: Update the axi write controller 
Do some refactoring and add a DMA beat counter.
 2016-05-27 14:13:55 +03:00
Istvan Csomortani c8d4f956e7 axi_dacfifo: Update the read back logic 
Update the readback logic of the FIFO. The controller uses a
relative address counter, which counts the DMA beats. The readback
logic uses the last value of that counter to define the wrapping
address. The aditional data from the last AXI burst, if there is any,
will be dropped.
 2016-05-27 14:13:55 +03:00
Istvan Csomortani 81ade7f26c axi_dacfifo: Fix resets 
DMA side: axi_resetn is used to reset the address counters
DAC side: GT tx_rst is used to reset the last_address register
 2016-05-27 14:13:55 +03:00
Istvan Csomortani e855ef38f4 axi_dacfifo: Initial commit 
AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
 2016-04-19 11:28:33 +03:00