Commit Graph

6080 Commits (318523579faad68dd4ac9aba44a3e4e42a2c0c12)

Author SHA1 Message Date
Laszlo Nagy daba543797 ad9082_fmca_ebz: Readme.md: Remove AD9081 from parts 2021-11-15 13:59:26 +02:00
Laszlo Nagy fe9afd4392 ad9208_dual_ebz: Readme.md: Remove invalid product page
Product page on analog.com does not exists
2021-11-15 13:59:26 +02:00
Laszlo Nagy b25c37a8cc axi_adrv9001/intel: Add dummy parameters to match Xilinx interface
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-12 14:09:14 +02:00
Laszlo Nagy 2386abb89c ad_quadmxfe1_ebz : Add readme file 2021-11-12 14:08:56 +02:00
stefan.raus adad6c930d ad9081_fmca_ebz_qsys.tcl: Add RX_LANE_RATE and TX_LANE_RATE parameters
For ad9081/a10soc project, the RX_LANE_RATE and TX_LANE_RATE were computed
from SAMPLE_RATE. Remove SAMPLE_RATE and add RX_LANE_RATE and TX_LANE_RATE
as parameters. Update also computation examples from comments.

Signed-off-by: stefan.raus <stefan.raus@analog.com>
2021-11-12 13:04:57 +02:00
Laszlo Nagy fe58a5fb47 adrv9009zu11eg/adrv2crr_fmcomms8: Add clock buffers for core clocks
The IBUFGDS primitive is deprecated in UltraScale devices.

Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-11 17:33:10 +02:00
Laszlo Nagy 1cd866445e ad_quadmxfe1_ebz: Initial version
Parametrizable project for the QUAD-MxFE platform ADQUADMXFE1EBZ,
ADQUADMXFE2EBZ, ADQUADMXFE3EBZ

Default mode set to:
  TX JESD204C MODE 11, M=16, L=4
  RX JESD204C MODE 4, M=8, L=2

For 204C 64B66B mode as physical layer the Xilinx Phy is uesd.
2021-11-10 14:03:34 +02:00
Laszlo Nagy 36d0a8b3e8 library:util_pad: Initial version
Data to DMA/system memory must be presented in widths of multiple of 8 bits,
however this padding is not optimal if is done in the transport layer
since this will affect the DAC/ADC FIFO or offload storage.

This utility block adds or removes padding from sample stream in case the
sample with is not multiple of 8 bits, and can be placed between the DMA
and FIFO/Offload blocks.
2021-11-10 14:03:34 +02:00
Laszlo Nagy cb8cf4b3d2 jesd204/scripts: Helper procedure for TPL width calculation 2021-11-10 14:03:34 +02:00
Laszlo Nagy 5dd9fd4832 axi_dmac: Allow wider FIFO/AXI Stream interface
On large projects with multiple channels the databus on the FIFO/AXI
stream interface can get wider that 1024 bits.

This commit allows a wider range for all the interfaces,
in case for the memory mapped interfaces where the range is 32-1024 the
user selects a bus width out of range that will be handled by the IPI.
2021-11-10 14:03:34 +02:00
Robin Getz 63b6711cfa start adding some doc to the ./projects directory
This adds a Readme.md to each project directory with pointers to project
documentation in the wiki, and the drivers (if they exist). This will
help with some autogenerated doc in the wiki, that is generated with the
innovatily named "wiki_summary.sh" shell script that parses through
these Readme.md files, and generates a summary table.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Iacob Liviu Mihai <liviu.iacob@analog.com>
2021-11-10 14:01:06 +02:00
LIacob106 58c1d2e3b2 projects: fixed xcvr clocks that generated critical warning 2021-11-09 12:40:14 +02:00
Laszlo Nagy 5ad40b29e5 adrv9001/zed: Use global clock buffers for better fit the design
Occasionally with zed, the implementation failed at the placement stage where
the tool could not fit the logic cells inside a single clock region,
constraint required by the usage of regional clock buffers.

This commit allows the usage of the global clock buffers which help the tool
in such cases and allow a larger application logic to be implemented in fabric.
2021-11-08 13:53:51 +02:00
Laszlo Nagy fcb16daf5b axi_adrv9001: Add the option of global clock buffers on 7 series
Using global clock can help placement issues where the logic does not fits in one
clock region.
2021-11-08 13:53:51 +02:00
Laszlo Nagy 7112fbce7e library/scripts/adi_xilinx_device_info_enc.tcl: Add K26 support 2021-11-08 09:23:02 +02:00
Nicola Corna 5d7f4672f5 axi_i2s_adi: initialize cdc_sync_stage0_tick bits to '0' 2021-11-08 08:52:01 +02:00
Nicola Corna 18ab43b5a1 axi_hdmi_tx: Add UltraScale+ architecture to Verilog 2021-11-08 08:52:01 +02:00
Dan Hotoleanu 457c5f7d86 fmcjesdadc1: Fix ad9250 core parameters settings
Fix CONVERTER_RESOLUTION parameter setting for ad9250. Also deleted the
setting of BITS_PER_SAMPLE and DMA_BITS_PER_SAMPLE for ad9250 since they
are set by default to the desired values.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-11-04 12:18:06 +02:00
Dan Hotoleanu a381fe3e92 ad_ip_jesd204_tpl_adc: Add value of 14 to CONVERTER_RESOLUTION parameter
Added new allowed value of 14 for the CONVERTER_RESOLUTION parameter.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-11-04 12:18:06 +02:00
stefan.raus 3c07861ee8 generate_xml.sh: Replace < and > in error message
Replace < with &lt; and > with &gt; in ERRS to not broke created xml.

Signed-off-by: stefan.raus <stefan.raus@analog.com>
2021-11-03 15:22:45 +02:00
Stanca Pop bcf5abb2fe xmicrowave: Initial commit 2021-11-02 15:44:47 +02:00
hotoleanudan 1bc8a41aea
vc709_carrier: Add vc709 carrier (#788)
Added vc709 carrier to the projects/common folder location.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-11-02 12:05:42 +02:00
Laszlo Nagy 70cc53bbc8 ad_ip_jesd204_tpl_dac: Move external dac sync bit 2021-10-27 18:36:47 +03:00
Laszlo Nagy 7b0922e4dc library/common/up_adc_common.v: Remove tabs 2021-10-27 18:36:47 +03:00
Laszlo Nagy a9c9636780 library/common/up_dac_common.v: Cleanup spaces 2021-10-27 18:36:47 +03:00
Filip Gherman 9b7c2852b6 adxcvr: Increase version to 17.5.a
Add suport for XCVR phase adjust buffer status:
   - Expose TXBUFSTATUS and RXBUFSTATUS
   - Create RXBUFSTATUS_RST flag for clearing RXBUFSTATUS
2021-10-27 14:40:50 +03:00
Laszlo Nagy c5d216bba9 adrv9001/zcu102: Enable independent TX mode in CMOS
For CMOS case, lane rates are so low that reference clock of the source
synchronous interface can be routed on non-clock routes. The delays on
the clock line are adjusted by the digital interface tuning controlled
through software.

Lock down clock buffers on Rx and Tx interfaces, this avoids suboptimal
placement which causes large skew between clocks at the serdes pins.
2021-10-27 14:40:08 +03:00
Laszlo Nagy d493b724f2 axi_adrv9001/adrv9001_rx.v: Simplify clocking 2021-10-27 14:40:08 +03:00
Laszlo Nagy 03682f6193 projects/adrv9001/zcu102/lvds_constr.xdc: Fix timing constraints
1. Reduce max allowed skew between source synchronous clocks that can
occur due PCB differences. 250ps represents a difference more than an
inch.

2. In order to reduce skew between source synchronous clock and the
divided clock instruct the tool to use a common clock root for them.
2021-10-27 14:40:08 +03:00
David Winter 6a5d2f76d5 data_offload: Fix oversized TX input transactions
Signed-off-by: David Winter <david.winter@analog.com>
2021-10-27 14:26:22 +03:00
David Winter cd6024b341 Revert "data_offload: Fix oversized inputs in TX mode"
This reverts commit 0e8f55b2d7.
2021-10-27 14:26:22 +03:00
LIacob106 d4126739b4 projects: remove hardcoded div_clk from xcvr 2021-10-27 12:11:22 +03:00
sergiu arpadi 52df3c4937 ad463x_data_capture: Remove tb 2021-10-26 15:58:54 +03:00
sergiu arpadi cb861f5299 ad463x: Fix readme 2021-10-26 15:42:57 +03:00
LIacob106 076e81a17c library: Add link to wiki for IPs 2021-10-25 10:44:53 +03:00
Istvan Csomortani 15a6480601 ad4630_fmc: Initial commit 2021-10-18 16:13:31 +03:00
Istvan Csomortani 6a526f4bb6 ad463x_data_capture: Initial commit
IP required to support echo and master clock mode
2021-10-18 16:13:31 +03:00
Istvan Csomortani 5ac64b021f spi_engine_execution: Delete control loop-back in sdi_data_valid generation 2021-10-18 16:13:31 +03:00
sergiu arpadi 6570c23a76 axi_spi_engine: Add generic config params
The 4 parameters are added to facilitate transmiting project
related information to the software. They act as read-only
memory which is written in Vivado when the project builds.
Set 31 to SDI FIFO's almost full threshold
2021-10-18 16:13:31 +03:00
Istvan Csomortani f86ae28e50 spi_engine/data_reorder: Initial commit
In case of multiple SDI (MISO) lanes, the samples arrives in a parallel
fashion. For example in case of 4 MISO line, at the first latching clock
edge 4 bits of a sample will be saved, one bit into each shift register.

The data reorder module reconstruct the incoming samples from the AXI
stream of the offload module.
2021-10-18 16:13:31 +03:00
Istvan Csomortani 6565c5d018 library/tb: Improve run_tb.sh 2021-10-18 16:13:31 +03:00
Mihaita Nagy ff090b60ef daq2/zcu102: Fix the ad9144 data offload to use internal BRAM 2021-10-15 15:03:22 +03:00
Mihaita Nagy 3640c2b584 daq2/kcu105: Fix the ad9144 data offload to use internal BRAM 2021-10-15 15:03:22 +03:00
Mihaita Nagy 6ad54c1056 daq2/kc705: Fix the ad9144 data offload to use internal bram 2021-10-15 15:03:22 +03:00
Mihaita Nagy 907cd613aa daq2/zc706: Increase BRAM utilization to 52% 2021-10-15 15:03:22 +03:00
LIacob106 e34346360d scripts: Add logic for vivado version check 2021-10-12 14:34:11 +03:00
Laszlo Nagy 812baf9022 Revert "data_offload: Fix timing violation"
This reverts commit 1fe0d5f8e0.
2021-10-08 11:42:05 +03:00
Laszlo Nagy 5db7574dce scripts/adi_board.tcl: For older families stick with axi_interconnect
SmartConnect has higher resource utilization and worse timing closure
that makes several zed based projects to fail timing.
2021-10-07 14:18:49 +03:00
Filip Gherman dbd5ffe4ed jesd204_rx: fixed makefile 2021-10-07 12:48:08 +03:00
Laszlo Nagy 0c6c28ed84 jesd204/ad_ip_jesd204_tpl : Add support for 12 lanes 2021-10-06 15:49:56 +03:00