Add missing timing exceptions on paths between the DMA and DDR clock
domains. All these paths are properly synchronized using CDC in the HDL,
but are missing timing exceptions in the XDC file. This can lead to timing
errors when building a design using the axi_adc_fifo.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Export the reset signal for the link clock domain. This can be used by
external logic that is in the link clock domain to reset itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Enabling the phase alignment mode of the FPLL seems to break manual
re-calibration, which is required when changing the lane rates. The
calibration seems to select the wrong VCO frequency band and the PLL no
longer locks.
Disable phase alignment mode for now, this has a negative effects on
deterministic latency, but it is better than not working at all.
Waiting for feedback from Altera/Intel on how to make manual re-calibration
work in phase alignment mode.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
To be able to check the FPLL re-configuration arbitration status from
software enable the avmm_busy flag in the register map.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The DEGLITCH state of the RX state machine is a workaround for misbehaving
PHYs. It is an internal state and an implementation detail and it does not
really make sense to report through the status interface.
Rework things so that DEGLITCH state is reported as part of the CGS state
on the external status interface.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The current layout of the debug ID register assumes that the ID_WIDTH is 3.
Change things so that the padding 0 width depends on the ID_WIDTH
parameter so that we end up with the same register layout regardless of the
value of ID_WIDTH.
Also split things into two registers, this allows for an ID_WIDTH up to 8
(which should hopefully be enough for all practical applications).
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Redesign the axi_dacfifo, to increase the supported datarates.
Major modifications:
+ The FIFO consist of two module: WRITE and READ. The axi_dacfifo_dac
was deprecated.
+ Both the AXI write and AXI read transaction are controlled by two
FSM, to increase redability of the code.
+ Support all the possible burst lengths [0..225], handles the last
fractional burst on both sides correctly.
+ Common reset architecture throughout the design, all the internal
registers and memories are reset on the posedge of dma_xfer_req
+ Delete all Altera related sources, for Altera projects
avl_dacfifo should be used.
WIP: foobar
[WIP]axi_dacfifo: Update
axi_dacfifo: Few minor updates, almost working state
Add support for the AD-FMCDAQ2-EBZ on the Arria10 SoC development board platform.
In its default configuration the Arria10 SoC development board is not fully
compatible with the AD-FMCDAQ2-EBZ and a slight rework is necessary,
changing the position of four 0 Ohm resistors:
R610: DNI -> R0
R611: DNI -> R0
R612: R0 -> DNI
R613: R0 -> DNI
R620: DNI -> R0
R632: DNI -> R0
R621: R0 -> DNI
R633: R0 -> DNI
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Rework the peripheral address to match the updated semantics of
ad_cpu_interconnect, which expects that the addresses are in the range of
0x00010000 - 0x001fffff. This includes updating the base addresses as well
as compressing the used address range to fit into the 2Mb window.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add a wrapper module for Altera/Intel platforms that instantiates and
connects all the components required to for a JESD204 link.
The following components are created:
* Transceiver for each lane
* Transceiver lane PLL (TX only)
* Transceiver reset controller
* Link PLL
* JESD204 link layer processing
* JESD204 link layer processing control interface
* axi_adxcvr link management peripheral
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add a wrapper that instantiates the Arria10 Native PHY and configures it
for JESD204 operation. The datapath width is set to 4 octets per beat.
The maximum lane rate that is achievable with hard-logic PCS included in
the PHY is below the requirements of the JESD204 for some of the PHY speed
grades. For projects that require a lane rate that is higher than what the
hard-logic PCS can support a soft-logic PCS module can be instantiated. The
external interface of the jesd204_phy is identical regardless of whether
soft- or hard-logic PCS is used.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Istvan Csomortani
AndreiGrozav
Lars-Peter Clausen
Adrian Costina
Rejeesh Kutty