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Author SHA1 Message Date
Iulia Moldovan 961ebe0cc2 projects: Update .v files according to guideline 
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
 2022-06-28 18:06:56 +03:00
Sergiu Arpadi 3241924d14 sysid_intel: Added sysid to intel projects 2020-09-11 15:46:06 +03:00
Istvan Csomortani 253a8cb6ee dac_fmc_ebz/a10soc: Tool expect that all config parameters exists on top entity 2020-03-17 17:25:02 +00:00
Laszlo Nagy 35412c81a9 dac_fmc_ebz: drive spi_en pin automatically based on FMC board selected 
spi_en is active ...
   ... high for AD9135-FMC-EBZ, AD9136-FMC-EBZ, AD9144-FMC-EBZ,
   ... low for AD9171-FMC-EBZ, AD9172-FMC-EBZ, AD9173-FMC-EBZ
 2020-03-03 15:49:30 +02:00
Lars-Peter Clausen 6d31a437aa dac_fmc_ebz: Add initial Arria10 SoC support 
Add support for the Arria 10 SoC development kit to the dac_fmc_ebz
project.

This allows to use the following FMC boards on the Arria 10 SoC development
Kit carrier:
  * AD9135-FMC-EBZ
  * AD9136-FMC-EBZ
  * AD9144-FMC-EBZ
  * AD9152-FMC-EBZ
  * AD9154-FMC-EBZ
  * AD9171-FMC-EBZ
  * AD9172-FMC-EBZ
  * AD9173-FMC-EBZ

Note that the board in its default configuration is not fully compatible with the
mentioned FMC boards and some slight re-work moving some 0 Ohm resistors is
required. The rework concerns the LA01 and LA05 pins, which by default are
not connected to the FPGA. The changes required are:

  LA01_P_CC
    R612: R0 -> DNI
    R610: DNI -> R0
  LA01_N_CC
    R613: R0 -> DNI
    R611: DNI -> R0
  LA05_P
    R621: R0 -> DNI
    R620: DNI -> R0
  LA05_N
    R633: R0 -> DNI
    R632: DNI -> R0

The main differences between AD9144-FMC-EBZ and AD9172-FMC-EBZ are:
  * The DAC txen signals are connected to different pins
  * The polarity of the spi_en signal is active low instead of active high
  * The maximum lane rate is up to 15.4 Gpbs

To accommodate this all 4 possible txen signals as well as the spi_en
signal are connected to GPIOs. Software can decide how to use them
depending on which FMC board is connected.

Note that each carrier has a maximum supported lane rate. Modes of the
AD9172 (and similar) that exceed the carrier specific limit can not be used
on that carrier. The limits are as following:
  * A10SoC: 14.2 Gbps
 2019-06-06 11:45:05 +03:00