711cb66985
adrv9371x: Write parameter as hexa value to clear Vivados ambiguity between decimal and binary
2017-07-14 10:20:57 +03:00
0360e8587e
Connect JESD204 interrupts
...
Connect the ADI JESD204 link layer peripheral interrupt signals in all
projects.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-05 14:37:50 +02:00
6ebef5dde0
make: Update make files
2017-06-26 15:51:19 +01:00
1541943ff2
adrv9371_alt: Delete the fifos from the RX path
...
+ Delete the rx_fifo and rx_os_fifo from the RX datapath
+ Change the receive DMA's source interface type to wr_fifo
2017-06-22 11:58:10 +01:00
40bfd0380e
adrv9371x/a10gx- alt 16.1 updates
2017-06-07 09:19:14 -04:00
b7ca17f02b
scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects
2017-06-07 12:06:50 +03:00
dd48929327
hdlmake.pl - updates
2017-06-06 12:25:35 -04:00
f278b6e6c9
adrv9371x/a10soc- constraints/project updates
2017-06-06 12:23:26 -04:00
e34057c2b2
adrv9371x/a10gx- constraints/project updates
2017-06-06 12:22:31 -04:00
578ccaaa44
adrv9371x:a10gx, update create project command and Makefile
2017-06-06 17:30:12 +03:00
0bd22e78d9
altera- adi-project-create version
2017-06-05 15:24:35 -04:00
50cdb6db67
Merge branch 'jesd204' into dev
2017-05-31 20:44:32 +03:00
84b2ad51e2
license: Add some clarification to the header license
2017-05-31 18:18:56 +03:00
85ebd3ca01
license: Update license terms in hdl source files
...
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
4c998d1e18
make: Update make files
2017-05-25 15:12:17 +03:00
a7e72245ff
adrv9371: Convert to ADI JESD204 core
...
Convert the ADRV9371 project to the ADI JESD204 link layer cores. The
change is very straight forward, but a matching change on the software side
is required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
01aea161fa
Create CDC helper library
...
Move the CDC helper modules to a dedicated helper modules. This makes it
possible to reference them without having to use file paths that go outside
of the referencing project's directory.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
4f0accbbfa
adrv9371x fix dacfifo name
2017-05-18 12:54:14 -04:00
ff7dc41066
alt-jesd- constraints update
2017-05-18 09:55:24 -04:00
f8f7bdd6a6
a10soc- fix version check
2017-05-17 16:26:28 -04:00
9055774795
all: Update license for all hdl source files
...
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.
New license looks as follows:
Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.
Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
(at the option of the user):
1. The GNU General Public License version 2 as published by the
Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
OR
2. An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
ebeebdddf0
altera- infer latest versions
2017-05-12 13:40:14 -04:00
ef97c1e375
adrv9371x/a10soc: Fix constraints
...
Signed-off-by: Istvan Csomortani <istvan.csomortani@analog.com>
2017-05-02 14:37:11 +03:00
b3ce821311
change pl ddr clock to 1G
2017-05-01 09:35:10 -04:00
cfd4e006b3
hdlmake updates
2017-04-25 15:46:26 -04:00
6ed721ee66
adrv9371/a10soc: Integrate the avl_dacfifo into project
2017-04-21 13:27:35 +03:00
942d69a30c
Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU
2017-04-18 10:57:16 +03:00
1c23cf4621
all: Update verilog files to verilog-2001
2017-04-13 11:59:55 +03:00
bc9483c5a2
Ip automatic version: Update ad*/common/ad*_bd.tcl
...
ad6676evb/common/ad6676evb_bd.tcl
ad7616_sdz/common/ad7616_bd.tcl
ad7768evb/common/ad7768evb_bd.tcl
ad9265_fmc/common/ad9265_bd.tcl
ad9434_fmc/common/ad9434_bd.tcl
ad9467_fmc/common/ad9467_bd.tcl
ad9739a_fmc/common/ad9739a_fmc_bd.tcl
adrv9371x/common/adrv9371x_bd.tcl
adv7511/common/adv7511_bd.tcl
fmcadc4/common/fmcadc4_bd.tcl
2017-04-10 18:52:37 +03:00
8eb1dd0a8b
adrv9371x/altera- xilinx/chip-select consistency
2017-03-29 12:59:09 -04:00
deb8635854
adrv9371x/altera- gpio equivalency fix
2017-03-27 16:37:55 -04:00
8f1564a9c4
adrv9371x/a10gx- gpio matching
2017-03-27 13:51:45 -04:00
cc6bf53d98
adrv9371x/a10soc- altera reset synchronizer false path?
2017-03-23 09:46:40 -04:00
8063ba2b66
make updates
2017-03-20 16:05:18 -04:00
d08d1d5a1b
adrv9371x ,daq3, fmcomms7, fmcomms11: add dac_fifo missing reset connection
2017-03-10 14:20:42 +02:00
3fa9a30f0e
a10soc/plddr4- lower mem clk to meet timing
2017-03-06 14:12:25 -05:00
936c441763
adrv9371x- dacfifo bypass-gpio control
2017-03-06 10:35:09 -05:00
762276a880
adrv9371x- dacfifo changes
2017-03-06 10:33:52 -05:00
ec89b1a45f
altera/adrv9371x- add dacfifo
2017-03-01 15:52:07 -05:00
bc6a09c828
adrv9371x/a10soc- dacfifo added
2017-03-01 15:35:04 -05:00
0cc5130c9a
adrv9371x: Set XCVR Tx/RX clk/data voltage levels at 1V
2017-03-01 11:32:17 +02:00
dc168f41fe
adrv9371_a10soc: Fixed port assignments
2017-03-01 11:32:17 +02:00
fb4a583613
projects/system_bd- adc/dac fifo board designs
2017-02-27 16:06:39 -05:00
6b1a8852a9
dacfifo- bypass port name change
2017-02-27 16:06:39 -05:00
0059c907ea
adrv9371: Drive the TX DMA interface with sys_dma_clk
2017-02-24 15:50:12 +02:00
c598e84258
remove processing order (no clock def dependency)
2017-02-22 16:02:08 -05:00
edd5e9570f
file renamed; sed output; fingers crossed
2017-02-22 15:56:37 -05:00
62792ddaed
adrv9371x: Change the axi_adxcvr cores addresses
...
Because the S_AXI interface of the axi_adxcvr core was infered
using the process adi_ip_properties, the interface address range
has changed from 4k to 64k. As a result, all the addresses of
the axi_adxcvr cores were changed and realigned.
2017-01-19 15:23:03 +02:00
4a783d523d
projects/altera* - default & common qsys commands
2016-12-20 16:27:44 -05:00
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
2d7fb03b93
adrv9371x/a10gx- fix os xcvr parameters
2016-12-06 12:31:40 -05:00
e5d3bae54d
projects/ad6676-adrv9371: xcvr updates
2016-11-23 11:06:22 -05:00
7008c641b5
axi_adrv9371/zc706: Constraints update
...
From source *jesd_rstgen* is a false path for TX and RX_OS too.
2016-11-11 10:35:09 +02:00
35c2dd5d6d
adrv9371x/zc706: Fix constraints
2016-11-09 16:34:08 +02:00
ce3b6a2d3f
adrv9371x: Updated constraints for altera projects
2016-11-04 18:20:46 +02:00
671a547c2b
hdlmake- updates
2016-11-01 12:41:25 -04:00
50552ce7d6
adrv9371x- altera updates
2016-10-27 09:25:00 -04:00
f752f0c9d7
a10soc- xcvr updates
2016-10-27 09:25:00 -04:00
801f980aeb
adrv9371: Fix parameter name
2016-10-21 12:50:20 +03:00
cb97bc500a
hdlmake updates
2016-10-17 16:29:57 -04:00
7290bcc81a
hdlmake- updates
2016-09-29 11:50:58 -04:00
4950c6c773
adrv9371x - xcvr updates
2016-09-29 11:50:58 -04:00
e40311eee9
adrv9371x: A10soc, connected DMAs through 128 bit SDRAM0 port at 175MHz
2016-09-29 09:14:37 +01:00
f5809b8817
adrv9371x: a10soc, added adcfifos; connected the new reset to all peripherals; used the new f2sdram1 port
2016-09-24 10:09:05 +03:00
143423e3b9
adrv9371x: A10SOC, fix Makefile and system scripts to be compatible with altera
2016-09-21 18:13:02 +03:00
500d8bfb90
adrv9371x: A10GX, fix makefile and system_qsys.tcl script
2016-09-21 18:11:35 +03:00
16ee1336c3
Makefile: Update make files
2016-09-15 11:41:06 +03:00
521c41ce32
adrv9371x: Updated a10soc project. Common design differentiates between nios and a10soc carrier
2016-09-08 11:44:45 +03:00
d18f6aa816
adrv9371x: A10GX, added adcfifo
...
- connected dac dma to 133 MHz clock
- set explicit clock rate to xcvr reference clock bridge
2016-08-26 14:46:48 +03:00
3c6cfdc7b5
adrv9371x: A10GX, switched TX lanes
2016-08-24 18:06:14 +03:00
215edb11c6
adrv9371: A10GX, updated design
...
- disable reconfiguration for RX transceivers and enabled the reconfiguration for TX transceiver. They cannot be enabled at the same time at this point
- update FIFO SIZE to 16 for all DMAs
- updated memory connections to 256 bit and moved clock connection to 133 MHz, for all DMAs.
2016-08-23 18:25:48 +03:00
270f8a6bbe
adrv9371x: Updated project common
2016-08-22 16:58:21 +03:00
f697490de6
hdlmake- updates
2016-08-19 15:59:41 -04:00
41203d07e9
adrv9371x: A10GX, update SPI connection
2016-08-18 17:42:27 +03:00
03c83b59bf
adrv9371x/a10soc: Export axi_ad9371_s and xcvr_reconfig_avmm
2016-08-17 19:03:53 +03:00
ce1fed1ce6
dmafifo- adc/dac split
2016-08-16 12:54:39 -04:00
eb55f600fb
adrv9371x: Initial commit
...
-need to fix dc filter module for AD9371 / altera
2016-08-16 15:50:46 +03:00
5c27ccd1fa
adrv9371x: Added common qsys tcl
2016-08-16 15:34:10 +03:00
4658686ae1
adrv9371x/a10soc: Misc changes for being able to run Linux
2016-08-16 11:56:25 +03:00
39c1c83d00
adrv9371x/a10soc: Fix spi_csn assignment
2016-08-12 10:07:11 +03:00
0b0aa8e6c0
Makefile: Add MMU option to altera makefiles
2016-08-11 17:46:54 +03:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
e42b4ea378
hdlmake- updates
2016-08-04 13:28:25 -04:00
7ca8e10004
make: Update Make files
2016-08-01 14:24:48 +03:00
2e80dec513
adrv9371x/zc706: Update project with the new axi_dacfifo
2016-06-22 12:33:47 +03:00
eaf4d4a19d
makefile updates
2016-06-10 14:26:14 -04:00
f84fafaaac
adrv9371x/zc706: Fix system top
...
The dac_fifo_bypass gpio is an internal gpio only. No need for IOBUF.
2016-06-10 10:11:27 +03:00
3351ff607e
adrv9371x- need to investigate merge with avalon
2016-06-02 16:22:53 -04:00
c293c04634
hdl make updates
2016-06-01 13:53:09 -04:00
46b464ed72
adrv9371/a10soc- qsys updates
2016-06-01 13:48:51 -04:00
a958ef27da
adrv9371- qsys updates
2016-06-01 13:48:51 -04:00
5b2a90ffff
adrv9371- qsys
2016-06-01 13:48:51 -04:00
af45acfcb9
ad9371- qsys updates
2016-06-01 13:48:51 -04:00
1853c6921d
adrv9371x/zc706: Fix typo in system_top
2016-05-27 14:13:55 +03:00
a6fbf6c20b
adrv9371x: Update the Makefiles
2016-05-27 14:13:55 +03:00
32d46389f2
adrv9371x: Move GTs AXI interface to HP3
...
If the VDMA and the GTs AXI are connected to the same HP port, the
HDMI won't work on full resolution (1080p). Care should be taken, this can
affect the receive and observation paths (both are connected to HP2).
2016-05-27 14:13:55 +03:00
b452a8e2d4
adrv9371x: Connect bypass and data underflow
2016-05-27 14:13:55 +03:00
3859cba186
adrv9371x/zc706: Add PL_DDR FIFO to the design
2016-05-27 14:13:55 +03:00
0d1c4d232e
a10soc- updates-1
2016-05-20 16:14:57 -04:00
09520709b0
make updates
2016-05-20 12:35:45 -04:00
f92e8509bb
adrv9371x- added
2016-05-20 11:46:25 -04:00
Adrian Costina
Lars-Peter Clausen
Istvan Csomortani
Rejeesh Kutty
AndreiGrozav
dbogdan