Adrian Costina
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1fcaf8fb63
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fmcomms1: Updated AC701 project to meet timing. Reduced FIFO size for AD9643 DMA to 8
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2015-05-05 23:37:01 +03:00 |
|
Adrian Costina
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90a5bb81b6
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cftl_cip: Updated project to work with the new util_pmod_adc core
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2015-05-05 23:34:52 +03:00 |
|
Adrian Costina
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233cc111d2
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util_pmod_adc: Used generated clock for the ADC SPI. Works by default at 6.25MHz
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2015-05-05 23:33:13 +03:00 |
|
Adrian Costina
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95805f21fa
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adv7511: Fixed system_top for mitx045 board
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2015-05-05 10:08:11 +03:00 |
|
Adrian Costina
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3517b6941c
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adv7511:kcu105, axi_hdmi_tx, axi_spdif_tx constraints modified so they apply to ultrascale
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2015-05-05 10:06:26 +03:00 |
Rejeesh Kutty
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319f821fab
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zc706pr - makefile
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2015-05-04 13:41:03 -04:00 |
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Rejeesh Kutty
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ab85e2ba36
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zc706pr - 706 partial reconfiguration
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2015-05-04 12:36:57 -04:00 |
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Rejeesh Kutty
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e489090fbb
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scripts- initialize prcfg list
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2015-05-04 12:34:19 -04:00 |
|
Rejeesh Kutty
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2a8703763e
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zc706pr - 706 partial reconfiguration
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2015-05-04 12:33:28 -04:00 |
|
Rejeesh Kutty
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c3dd9258e7
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zc706: project mode
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2015-05-04 10:25:12 -04:00 |
|
Rejeesh Kutty
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62acd37fee
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zc706: project mode
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2015-05-04 10:25:07 -04:00 |
|
Rejeesh Kutty
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707b285669
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prcfg: bb def
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2015-05-04 10:24:13 -04:00 |
Istvan Csomortani
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e7a0da9089
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fmcomms2 : Verify the existence of the PR license
The fmcomms2 runs by default on PR mode, if the project script does not find a PR license, will implement just the default mode.
|
2015-05-04 15:12:38 +03:00 |
|
Rejeesh Kutty
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4bb26caa13
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itx045: default install
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2015-05-01 16:19:10 -04:00 |
|
Rejeesh Kutty
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ad551a0073
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itx045: updates
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2015-05-01 16:18:43 -04:00 |
|
Rejeesh Kutty
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aced144916
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itx045: updates
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2015-05-01 16:18:23 -04:00 |
|
Rejeesh Kutty
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ff443655ca
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itx045: add ps7 settings
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2015-05-01 16:17:59 -04:00 |
|
Rejeesh Kutty
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26fb85583b
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adi_project- prefix directory for gitignore & make clean
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2015-05-01 13:18:12 -04:00 |
|
Rejeesh Kutty
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ff985875a0
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gitignore: add non-project stuff
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2015-05-01 13:17:14 -04:00 |
|
Rejeesh Kutty
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00cafd4df0
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fmcomms2/zc706: add partial reconfiguration
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2015-05-01 12:23:18 -04:00 |
|
Rejeesh Kutty
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3641d8f714
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fmcomms2/zc706: add partial reconfiguration
|
2015-05-01 12:23:11 -04:00 |
|
Rejeesh Kutty
|
75a81d67d8
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fmcomms2/zc706: add partial reconfiguration
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2015-05-01 12:23:07 -04:00 |
|
Rejeesh Kutty
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0dc4c9cda9
|
adi_project: added partial reconfiguration
|
2015-05-01 12:21:59 -04:00 |
|
Rejeesh Kutty
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140c622c8b
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prcfg: common files
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2015-05-01 11:48:09 -04:00 |
|
Rejeesh Kutty
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a8d4c916c1
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fmcomms2_bd: remove axi3 switch
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2015-05-01 11:47:29 -04:00 |
|
Adrian Costina
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be32715ab3
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axi_adcfifo: Updated constraints
|
2015-04-30 14:23:24 +03:00 |
|
Adrian Costina
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3b58785368
|
daq1: Updated jesd reset connection. Fixed dmac async configuration. Updated zc706 constraints
|
2015-04-30 12:14:03 +03:00 |
|
Adrian Costina
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e332fa01c8
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ad6676evb, daq2, fmcadc2, fmcjesdadc1, usdrx1: Updated jesd reset connection
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2015-04-30 12:11:46 +03:00 |
|
Adrian Costina
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d623f77453
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axi_jesd_gt: Added rx_jesd_rst and tx_jesd_rst.
Resets for both up clock domain and rx clock domain are needed in some projects
|
2015-04-30 12:07:36 +03:00 |
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Adrian Costina
|
463c4d4d28
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util_wfifo: Added constraint for the resetn path
|
2015-04-30 12:05:02 +03:00 |
|
Adrian Costina
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392ba31a07
|
axi_hdmi_rx: Updated constraints
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2015-04-30 12:04:15 +03:00 |
dbogdan
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1df48a2e6e
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Add hdmiio_int pin.
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2015-04-29 18:50:28 +03:00 |
|
Adrian Costina
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19ef85cec3
|
vc707: Changed mig project to use BANK_ROW_COLUMN, as it seems this mode gives best performance
|
2015-04-28 17:15:58 +03:00 |
|
Adrian Costina
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288b9cccff
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Makefile: Added makefiles for imageon_loopback project. Updated axi_ad9152, util_gmii_to_rgmii, util_wfifo to include constraints file
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2015-04-28 15:22:37 +03:00 |
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Adrian Costina
|
252aa135eb
|
ad9739a: Changed dma and interconnect clock to 200mhz. Removed div_clk constraint, as it is autodetected
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2015-04-28 15:14:31 +03:00 |
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Adrian Costina
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a7a2d194e9
|
axi_jesd_gt: Switched rx_rst and rx_rst_done to up clock domain, to be compatible with xilinx JESD core
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2015-04-28 15:04:18 +03:00 |
|
Adrian Costina
|
3fdda617a4
|
fmcomms1: updated common, changed DMAC fifo size and wfifo reset signal source
- changed DMAC FIFO size to 16, as it should be large enough
- connected wfifo reset to adc_rst from axi_ad9643 core
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2015-04-28 14:58:04 +03:00 |
|
Adrian Costina
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37bfb2ef4b
|
ad9265: Updated common, wfifo is reset by the adc_rst signal from axi_ad9265 core
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2015-04-28 14:53:12 +03:00 |
|
Adrian Costina
|
c36186f75a
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axi_ad9643: Added adc_rst output
|
2015-04-28 14:52:24 +03:00 |
|
Adrian Costina
|
8ee3f64a65
|
axi_ad9265: Added adc_rst output
|
2015-04-28 14:51:14 +03:00 |
|
Adrian Costina
|
67c581cef8
|
util_wfifo: Updated to be used with adc_rst from the adc_clk clock domain
|
2015-04-28 14:50:00 +03:00 |
|
dbogdan
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1eebfd3155
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projects/imageon_loopback: Initial commit.
|
2015-04-28 10:32:28 +03:00 |
|
Adrian Costina
|
e51edfbadb
|
adv7511: KC705 mdio pin name fix
|
2015-04-27 11:21:36 +03:00 |
|
Adrian Costina
|
7e6f2bfa15
|
ad9265: Updated constraints file.
|
2015-04-27 11:20:42 +03:00 |
|
Adrian Costina
|
1ad87aa27c
|
util_wfifo: Added constraints
|
2015-04-27 11:19:56 +03:00 |
|
Adrian Costina
|
81d4e1d9b1
|
axi_clkgen: Updated constraints
|
2015-04-27 11:19:15 +03:00 |
|
Adrian Costina
|
d950f5ffcd
|
axi_ad9122: Updated constraints
|
2015-04-27 11:18:52 +03:00 |
|
Istvan Csomortani
|
9fba4cb2ef
|
util_dacfifo: Add support for Slave AXI stream interface.
The FIFO can be initialized through an AXI stream interface too.
|
2015-04-27 10:40:55 +03:00 |
Lars-Peter Clausen
|
3a02998e9a
|
axi_ad9152/axi_ad9152_ip.tcl: Fix typo
axi_ad9152_constr.v -> axi_ad9152_constr.xdc
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
|
2015-04-24 09:41:43 +02:00 |
|
Rejeesh Kutty
|
272148eee5
|
rfsom: sdio 50mhz
|
2015-04-23 15:30:50 -04:00 |