The constraint where added to remove timing problems on the reset path.
The constraint paths do not match anymore. The resets are used in a synchronous
way so we don't need the timing exceptions anyway.
Projects affected by this change:
- daq3
- adrv9739
- ad6676evb
- fmcadc5
- daq2/kcu105
- fmcadc2
- adrv9371x
- fmcomms11/zc706
- fmcjesdadc1
Fix the location assignment of the transceiver blocks to get the correct
lane mapping.
Note that the comments indicating the expected lane mapping are correct,
but the actual transceiver location assignments were not.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>