Commit Graph

2154 Commits (2b868c28575c104ea20f533bedff8102a7ed0118)

Author SHA1 Message Date
Lars-Peter Clausen d345a1e31a jesd204: jesd204_tx: Add dummy valid for the TX data interface
The Xilinx tools are quite forgiving when it comes to required signals on
standard interfaces, which is why it was possible to define a AXI streaming
interface without the required valid signal.

The Altera tools are more strict and wont allow this. Add a dummy valid
signal to the TX data interface to make the tools happy. For now the signal
does not do anything, in the future it might be used to detect an underflow
condition on the data interface and report this through the status
interface.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:08:27 +02:00
Lars-Peter Clausen f730f14d16 jesd204: ilas_mem: Rework to be more Altera friendly
Currently the ILAS memory for the receive register map uses a shift
register with variable tap output for storing the ILAS information. This
maps very efficiently onto the primitives found in Xilinx FPGAs. But there
is no equivalent primitive in Altera FPAGs resulting in increased
utilization from having to implement the structure in pure logic.

Change the ILAS memory so it uses a simple dual port RAM for storing the
data. This has slightly increased utilization on Xilinx platforms (but
still good enough) and highly decreased utilization on Altera platforms.

One side effect of this change is that since the RAM output is synchronous
reading the ILAS memory registers will take one extra clock cycle.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:05:16 +02:00
Lars-Peter Clausen 2d2477e552 util_cdc: Add helper function for creating constraints for the CDC blocks
Add a set of helper functions for the CDC library that creates the correct
constraints for the CDC blocks. This makes it easier to specify the
constraints in the individual user's SDC files.

This only works for Altera where full scripting capabilities are available
in the SDC files.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:05:16 +02:00
Lars-Peter Clausen 27d243ad14 adi_ip_alt.tcl: ad_ip_parameter: Allow to specify additional properties
Allow to specify additional properties when defining a IP parameter. The
properties take the form of a list of key value pairs. E.g.

ad_ip_parameter ... { \
  DISPLAY_NAME "Name" \
  DISPLAY_HINT "radio" \
}

This helps to reduce the amount of boilerplate when additional properties
need to be specified for a parameter.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:05:16 +02:00
Lars-Peter Clausen 9bf852fff2 adi_ip_alt.tcl: Allow to add TCL files to the fileset
TCL files can be helpful to automate certain tasks like creating timing
constraints. Add handling for them to the ad_ip_addfile function.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:05:16 +02:00
Lars-Peter Clausen 4acb91bedb jesd204: axi_jesd204_{rx,tx}: Add external link domain reset
Currently the reset for the link clock domain is generated internally in
the axi_jesd204_{rx,tx} peripheral. The reset is controlled by through the
register map.

Add an additional external reset for link clock domain. The link clock
domain is kept in reset if either the internal reset or the external reset
is asserted.

This for example allows the fabric to keep the domain in reset if the clock
is not yet stable.

The status of the external reset can be queried from the register map.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-18 18:25:12 +02:00
Lars-Peter Clausen cefb2b062e util_adcfifo: Remove always false check
dma_raddr is only incremented if it is less than dma_waddr_rel_s.
dma_waddr_rel_s is always less or equal to adc_waddr_rel << RATIO and
adc_waddr_rel is less than DMA_ADDR_LIMIT >> RATIO.

By induction we can conclude that this means that dma_raddr will always be
less then DMA_ADDR_LIMIT and the check for this will always evaluate to
false can be removed.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-18 09:26:24 +02:00
Lars-Peter Clausen a46b9cfa5a util_adcfifo: Fix data corruption at faster DMA clock rates
When the DMA clock to ADC data rate ratio exceeds a certain threshold it is
possible that an erroneous dma_waddr_rel toggle event is generated. This
causes the last address of the previous DMA transfer to be transferred to
the DMA domain. And the DMA side will start reading from the FIFO even
though data is not available yet.

This results in data corruption with the current transfer containing data
from the previous transfer.

The root cause here is that the toggle signal CDC synchronizer register are
reset in the DMA when a new transfer starts, but not in the ADC domain,
causing a potential mismatch and the incorrect toggle event. To fix this
remove the reset from the DMA side. This is OK since the registers are
self-resetting if the reset signal is asserted for more than 3 clock cycles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-18 09:26:23 +02:00
Lars-Peter Clausen f9fe66694d axi_logic_anlayzer: Fix trigger AND logic
AND logic means that all enabled triggers need to evaluate to true, others
are don't care. Fix the logic to behave accordingly.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 11:36:56 +02:00
Lars-Peter Clausen 42ff5d4f80 axi_streaming_dma_tx_fifo: Fix drain logic
At the moment the drain signal is always asserted when the controller is
enabled. This breaks backpressure and data is lost. The drain signal should
only be asserted when the controller gets disabled until the last beat of
the current DMA transfer.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-14 16:02:32 +02:00
Lars-Peter Clausen 38f495b2cf axi_i2s_adi: Make constraints work on UltraScale
The 'PRIMITIVE_SUBGROUP == flop' filter only works on 7-Series. Replace it
with 'IS_SEQUENTIAL' which works on both 7-Series and UltraScale.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-14 16:02:32 +02:00
Lars-Peter Clausen 3ab3d3d111 jesd204: axi_jesd204_rx_regmap_tb: Add missing dependency
Add missing source file dependency for the axi_jesd204_rx_regmap_tb.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-13 10:28:11 +02:00
Lars-Peter Clausen d807b10632 axi_dmac: axi_dmac_hw.tcl: Set associated reset and addressable point for the interrupt interface
Altera recommends to set those properties for better qsys integration.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-13 10:28:11 +02:00
Lars-Peter Clausen 8dc2161870 alt_mem_asym: Set read latency to 1 clock cycle
In its default configuration the ram_2port module as a read latency of 2
clock cycles. Both the read address as well as the output data are
registered.

This is not the behavior that is expected from the alt_mem_asym module and
causes incorrect behavior and data corruption in the util_adc_fifo.

Disable the data output register to get a read latency of 1 clock cycle.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-13 10:28:11 +02:00
Rejeesh Kutty bb660d8cf8 rfifo- drive valid outs 2017-08-10 11:23:40 -04:00
Rejeesh Kutty 8aba66477e util_adxcvr- defaults for es 2017-08-08 11:03:38 -04:00
Rejeesh Kutty 1c386d4d34 hdlmake.pl- updates 2017-08-07 16:09:20 -04:00
Lars-Peter Clausen 2b84fbb3b3 jesd204: Use consistent naming scheme for CDC blocks
Name all CDC blocks following the patter i_cdc_${signal_name}. This makes
it clear what is going on.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-07 17:44:23 +02:00
Lars-Peter Clausen 918f226f3b jesd204_tx: Use the CDC sync_bits helper to synchronize the SYNC~ signal
Use the CDC sync_bits helper to synchronize the asynchronous external SYNC~
signal into the link clock domain, rather than open-coding this operation.

This makes it more explicit what is going on.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-07 17:44:23 +02:00
Lars-Peter Clausen 350fbacf94 axi_jesd204_tx: Remove IRQ events for now
Which events will be exposed as IRQs and at what level of granularity will
need some additional through. Remove the two existing IRQ events for now
again. This will be added back later.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-07 17:44:23 +02:00
Lars-Peter Clausen 533b27bb13 axi_jesd204_tx: jesd204_up_tx: Use two dimensional array for up_cfg_ilas_data
The up_cfg_ilas_data signal is a two dimensional array. There are 4
register entries for each lane. Model it as such rather than compressing it
down to a one dimensional array. This makes accessing the individual
entries a bit more straight forward and the code clearer.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-07 17:42:56 +02:00
Lars-Peter Clausen 5d66f1d7bb jesd204_tx: Remove duplicated file
The ilas_cfg_static.v is part of the jesd204_tx_static_config module.
Somehow a copy of that file made it into the jesd204_tx module where it is
completely unused. Remove the duplicated file.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-07 17:42:17 +02:00
Lars-Peter Clausen a4641d99ba jesd204: rx_tb: Fix some incorrect signal connections
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-07 17:42:17 +02:00
Lars-Peter Clausen c51517f548 axi_adxcvr: Avoid implicit signal truncation warning
We know that NUM_OF_LANES will never exceed 255, but the tools don't know
and generate a warning about implicit signal truncation. Make the
truncation explicit to indicate that this is intentional.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-07 17:42:17 +02:00
Istvan Csomortani 9db58f5bb0 axi_ad9671: Fix typo 2017-08-07 10:54:45 +01:00
Istvan Csomortani 3b6f1e402a axi_ad9625: Fix typo 2017-08-07 10:53:57 +01:00
Istvan Csomortani fb6035f0dc util_cdc: Update to verilog-2001 coding standard 2017-08-07 11:26:17 +03:00
Istvan Csomortani 915fe036f2 util_axis_resize: Coding style updates
+ update to verilog-2001 coding standard
  + define RATIO outside the generate block
  + $clog2 macro is not supported by some tools, define function
locally
2017-08-07 11:23:57 +03:00
Istvan Csomortani 420245337d axi_ad9361: Update constraint file
Timing constraints, related to the PPS receiver, should be applied just
when the module is instantiated into the core.
2017-08-04 16:20:33 +01:00
Istvan Csomortani ed20d00f77 spi_engine: Add support for max 4 SDI lines 2017-08-04 14:49:17 +03:00
Adrian Costina 4d6c45eb83 axi_adc_decimate: Add correction at the end of the decimation chain
The CIC filter introduces different amplifications depending on the
decimation ratio. By adding a multiplier in the decimation chain
the amplification can be compensated
2017-08-04 14:28:37 +03:00
Lars-Peter Clausen fa9d94bfe8 avl_adxcvr: Perform octet order swap
The ADI transport layer peripherals expect the first octet to be in the
LSBs and the last octet to be in the MSBs. The Altera JESD204 core orders
the octets the other way around though, first octet in the MSBs and last
octet in the LSBS.

Currently this is handled by having each transport layer peripheral swap
the octets around when it is connected to the Altera JESD204 core.

Change this so that rather than having to do the data swizzling in every in
every transport layer peripheral perform it at the input/output of the link
layer peripheral inside the generated block.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-03 17:57:58 +02:00
Lars-Peter Clausen 69a23ecde3 avl_adxcvr: Simplify TX lane mapping
Currently the TX lane mapping is implemented by having to connect tx_phy_s_* to
the tx_ip_s_* and the tx_phy_d_* to the tx_ip_d_* signals in the system
qsys file in the desired order.

Re-work things so that instead the lane mapping is provided through the
TX_LANE_MAP parameter. The parameter specifies in which order logical lanes
are mapped onto the physical lanes.

The appropriate connections are than made inside the core according to this
parameter rather than having to manually connect the signals externally.

In order to generate a 1-to-1 mapping the TX_LANE_MAP parameter can be left
empty.

This change slightly reduces the boiler-plate code that is necessary to
setup the transceiver.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-03 17:57:58 +02:00
Adrian Costina f2240633b2 axi_dac_interpolate: Add correction at the begining of the interpolation chain
The CIC filter introduces different amplifications depending on the
interpolation ratio. By adding a multiplier in the interpolation chain
the amplification can be compensated
2017-08-03 17:21:37 +03:00
Istvan Csomortani 7cdb11cc34 axi_ad9361: Update the PPS receiver module
+ Add a HDL parameter for the PPS receiver module :
PPS_RECEIVER_ENABLE. By default the module is disabled.
  + Add the CMOS_OR_LVDS_N and PPS_RECEIVER_ENABLE into the CONFIG
register
  + Define a pps_status read only register, which will be asserted, if the free
running counter reach a certain fixed threshold. (2^28) The register can
be deasserted by an incomming PPS only.
2017-08-02 16:38:23 +01:00
Lars-Peter Clausen e644a99648 util_axis_fifo: Fix some data width mismatches
Make sure that the right hand side expression of assignments is not wider
than the target signal. This avoids warnings about implicit truncations.

None of these changes affect the behaviour, just fixes some warnings about
implicit signal truncation.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:22:29 +02:00
Lars-Peter Clausen 68c48d9bd4 util_axis_fifo: Switch to Verilog-2001 style parameter declaration
Verilog-2001 style module parameter declaration is the preferred coding
style for this repository.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:22:29 +02:00
Lars-Peter Clausen 95d530e7c9 axi_dmac: Set axi4lite address space size to 4k
The AXI specification that the minimum address space size is 4k, make sure
the axi_dmac adheres to this.

Internally the register space is still 2k. This means the upper and lower
2k of the axi4lite register space will map to the same internal registers.
Software must not rely on this and only access the lower 2k to enable
compatibility in case the internal space grows in the future.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:22:29 +02:00
Lars-Peter Clausen 1bf25edf77 axi_dmac: src_axi_stream: Terminate data mover m_axi_last signal
Terminate the m_axi_list signal of the data mover instance in the
src_axi_stream module. This avoids a warning about the port being
unconnected.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:22:29 +02:00
Lars-Peter Clausen 699d8970dd axi_dmac: axi_dmac_hw.tcl: Disable unused interfaces instead of not creating them
Currently the axi_dmac_hw.tcl script does not create interfaces if they
are not used in the current configuration. This has the disadvantage that
the ports belonging to these interfaces are not included in the generated
HDL wrapper. Which will generate a fair bunch of warnings when synthesizing
the HDL.

Instead always generate all interfaces, but disable those that are not used
in the current configuration. This will make sure that the ports belonging
to these interfaces are properly tied-off in the generate wrapper HDL.

This reduces the amount of false positive warnings generated and makes it
easier to spot actual issues.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:22:29 +02:00
Lars-Peter Clausen 834eb6aaa5 axi_dmac: dest_axi_mm: Use fixed wstrb signal
The DMAC currently doesn't support transfers where the length is not a
multiple of the bus width. When generating the wstrb signal we do pretend
though that we do and dynamically generate it based on the LSBs of the
transfer length.

Given that the other parts of the DMA don't support such transfers this is
unnecessary though. So remove it for now and replace it with a constant
expression where wstrb is always fully asserted.

The generated logic for the wstrb signal was quite terrible, so this
improves the timing of the core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:22:29 +02:00
Lars-Peter Clausen aeabe91144 axi_dmac: Comment out unused src_response interface
Currently the read side of the src_response interface is not used. This
leads to warnings about signals that have a value assigned but are never
read.

To avoid this just comment out all signals that are related to the
src_response interface for now.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:22:29 +02:00
Lars-Peter Clausen 16bd0c3894 axi_dmac: Fix some data width mismatches
Make sure that the right hand side expression of assignments is not wider
than the target signal. This avoids warnings about implicit truncations.

None of these changes affect the behaviour, just fixes some warnings about
implicit signal truncation.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:22:29 +02:00
Lars-Peter Clausen de4fe30238 library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size
The external s_axi_{awaddr,araddr} signals that are connect to the core
have their width set according to the specified size of the register map.

If the s_axi_{awaddr,araddr} signal of the core is wider (as it currently
is for many cores) the MSBs of those signals are left unconnected, which
generates a warning.

To avoid this make sure that the signal width matches the declared register
map size.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:21:25 +02:00
Lars-Peter Clausen b582b9ed99 util_upack: util_upack_hw.tcl: Disable unused interfaces instead of not creating them
Currently the util_upack_hw.tcl script does not create interfaces if they
are not used in the current configuration. This has the disadvantage that
the ports belonging to these interfaces are not included in the generated
HDL wrapper. Which will generate a fair bunch of warnings when synthesizing
the HDL.

Instead always generate all interfaces, but disable those that are not used
in the current configuration. This will make sure that the ports belonging
to these interfaces are properly tied-off in the generate wrapper HDL.

This reduces the amount of false positive warnings generated and makes it
easier to spot actual issues.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:21:02 +02:00
Lars-Peter Clausen c9f46b20e7 util_cpack: util_cpack_hw.tcl: Disable unused interfaces instead of not creating them
Currently the util_cpack_hw.tcl script does not create interfaces if they
are not used in the current configuration. This has the disadvantage that
the ports belonging to these interfaces are not included in the generated
HDL wrapper. Which will generate a fair bunch of warnings when synthesizing
the HDL.

Instead always generate all interfaces, but disable those that are not used
in the current configuration. This will make sure that the ports belonging
to these interfaces are properly tied-off in the generate wrapper HDL.

This reduces the amount of false positive warnings generated and makes it
easier to spot actual issues.

While we are at it also use a loop to create the interfaces since they all
follow the same pattern.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:21:02 +02:00
Lars-Peter Clausen 154e40eaaa axi_ad9144: axi_ad9144_hw.tcl: Disable unused interfaces instead of not creating them
Currently the axi_ad9144_hw.tcl script does not create interfaces if they
are not used in the current configuration. This has the disadvantage that
the ports belonging to these interfaces are not included in the generated
HDL wrapper. Which will generate a fair bunch of warnings when synthesizing
the HDL.

Instead always generate all interfaces, but disable those that are not used
in the current configuration. This will make sure that the ports belonging
to these interfaces are properly tied-off in the generate wrapper HDL.

This reduces the amount of false positive warnings generated and makes it
easier to spot actual issues.

While we are at it also use a loop to create the interfaces since they all
follow the same pattern.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:21:02 +02:00
Lars-Peter Clausen 97083a9766 axi_ad9144: Avoid implicit signal truncation warning
The width of a ternary operator expression is the width of the wider of the
two selectable expression. This means the right side expression of the
tx_data assigment is always 256 bits. This generates an implicit truncating
warning if the tx_data signal itself is only 128 bits.

To avoid this slightly reformulate the expression to yield the correct
width depending on the configuration.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:20:42 +02:00
Lars-Peter Clausen 99a08a7b90 util_adcfifo: Avoid implicit signal truncation warning
The width of a ternary operator expression is the width of the wider of the
two selectable expression. This means depending on the selected DMA_RATIO
the right side expression of the dma_waddr_rel_s assignment can be up to
three bits wider than the dma_waddr_rel_s signal. This generates an
implicit truncation warning.

Slightly reformulate the expression without the use of the ternary operator
to avoid this warning.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:18:40 +02:00
Lars-Peter Clausen 26641576d4 axi_ad9680: axi_ad9680_hw.tcl: Fix typo
The signal is called adc_clk and not adc_clock. None of the designs is
currently using the signal, so this hasn't been an issue other that it
generates a warning.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:18:40 +02:00
Lars-Peter Clausen ce32b4a9b7 axi_adxcvr: Avoid warning about unknown synthesis attribute
Comments starting with the word altera are interpreted by the Altera tools
to be synthesis attribute assignments. In this case this is just a generic
comment though which results in a warning that the synthesis attribute is
unknown.

Slightly reword the comment to avoid this. This is not pretty, but better
than having the false positive warning show up in the log.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:18:40 +02:00
Rejeesh Kutty c1e990b575 ad9361/sw- current sw requires clock edge swap 2017-07-31 14:48:25 -04:00
Rejeesh Kutty 4faa622f43 library/ad9361- gps_pps default value 2017-07-31 09:14:45 -04:00
Rejeesh Kutty adcd092ba3 library/ad9361- add pps module 2017-07-31 09:06:50 -04:00
Rejeesh Kutty 9f9955a84c hdlmake.pl updates 2017-07-31 09:02:12 -04:00
Rejeesh Kutty d3050abd3e rfifo/upack- changes 2017-07-28 16:18:54 -04:00
Rejeesh Kutty 5751cd30dc util_upack- port updates 2017-07-28 15:38:33 -04:00
Rejeesh Kutty 8a88d94553 ad_mem- syntax error fix 2017-07-28 15:26:48 -04:00
Rejeesh Kutty e9d8b969d6 util_rfifo- add valid turnaround 2017-07-28 15:26:48 -04:00
Rejeesh Kutty f81494f6c8 util_upack- add valid turnaround 2017-07-28 15:26:48 -04:00
Lars-Peter Clausen d7e87a60a9 Remove executable flag from non-executable files
All of these files are source code and are not executable standalone.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 17:56:07 +02:00
Lars-Peter Clausen f0655e63a6 avl_adxcvr: Derive PLL and core clock frequency from lane rate
The PLL frequency must be half of the lane rate and the core clock rate
must be lane rate divided by 40. There is no other option, otherwise things
wont work.

Instead of having to manually specify PLL and core clock frequency derive
them in the transceiver script. This reduces the risk of accidental
misconfiguration.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 15:11:08 +02:00
Lars-Peter Clausen a0f4adabd0 avl_adxcvr: Fix core clock bridge frequency
The clock bridge expects the clock rate to be specified in Hz, but
$m_coreclk_frequency is in MHz. Do the appropriate conversion.

Nothing seems to rely on the clock bridge reporting the correct frequency
at the moment, so this is only a cosmetic change.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 15:11:08 +02:00
Istvan Csomortani 6a84b8b5a1 license: Update old license headers 2017-07-28 12:53:58 +01:00
Istvan Csomortani 115c8f2ba6 license: Update old license headers 2017-07-28 12:47:14 +01:00
Adrian Costina 289b170dfd axi_ad9361: Fix altera lvds interface, reverting to an older working version 2017-07-28 10:09:17 +01:00
Istvan Csomortani 8ffc35735a axi_ad9361: ad_pps_receiver integration
The ad_pps_receiver is instantiated at the top of core.
The rcounter is placed into adc/dac_common registers space, at the
address 0x30 (word aligned).
The interrupt mask is placed into adc/dac_common, at the address 0x04
(word aligned). Because the core has an instance of both modules, the
interrupt masks are OR-ed together.
2017-07-28 07:57:13 +01:00
Istvan Csomortani c7304922d5 ad_pps_receiver: Initial commit
Add a module to receive 1PPS signal from a GPS module. The module has a
free running counter, which runs on the device's interface clock. The
counter value is latched into a register each time when a 1PPS arrives.
An interrupt signal is also generated in every 1PPS.
2017-07-28 07:46:58 +01:00
Adrian Costina 6882d8a59d util_clkdiv: Added altera version 2017-07-27 13:38:09 +01:00
Lars-Peter Clausen 367d2d58e7 jesd204: axi_jesd204_rx_regmap_tb: Check ILAS memory register
Add a check to RX register map to confirm that the ILAS memory registers
return the correct values after the ILAS data has been received.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-27 10:48:43 +02:00
Rejeesh Kutty 0aafd049c9 hdlmake.pl- remove ad_lvds 2017-07-26 10:32:44 -04:00
Rejeesh Kutty 893af8d3e6 library & projects- ad_lvds/ad_data replace 2017-07-26 10:31:48 -04:00
Rejeesh Kutty d4820dd55a library- remove ad_cmos_* 2017-07-26 10:20:39 -04:00
Rejeesh Kutty f26c1de38a ad9361/xilinx/lvds_if- fix frame check 2017-07-25 16:37:01 -04:00
Rejeesh Kutty 704512f0d4 library/xilinx/common- add iodelay group 2017-07-25 10:22:52 -04:00
Rejeesh Kutty 3eeba8273a hdlmake.pl/fmcomms2- updates 2017-07-24 16:33:40 -04:00
Rejeesh Kutty ff50963c7f axi_ad9361- altera/xilinx reconcile- may be broken- do not use 2017-07-24 16:28:50 -04:00
Rejeesh Kutty b65802ee1e library/xilinx- lvds/cmos integration 2017-07-24 16:28:50 -04:00
Rejeesh Kutty 206ea1f70a ad9361/xilinx- missing up_rstn 2017-07-24 15:52:00 +01:00
Rejeesh Kutty 247e540cf0 hdl/library- fix syntax errors/synthesis warnings 2017-07-24 15:31:22 +01:00
Lars-Peter Clausen 34e8309695 up_clock_mon: Explicitly truncate d_count during up_d_count assignment
The MSB of the d_count signal is used as a overflow marker to stop the
counter from incrementing in the monitored clock domain. It is not exported
through the register map and truncated when assigned to the up_d_count
signal.

Make the truncation explicit to make it clear that this is not a mistake
and to avoid warnings about implicit truncation.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-24 15:28:19 +01:00
Lars-Peter Clausen 9b37e441f4 jesd204: jesd204_up_common: Rename clock monitor instance to i_clock_mon
The generic Altera clock monitor constraints expect the instance to be
called i_clock_mon. Adjust the code accordingly.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-24 15:27:52 +01:00
Lars-Peter Clausen b03139e59e jesd204: jesd204_up_ilas_mem: Fix blocking assignment
In this particular case the behaviour is the same with non-blocking and
blocking assignments, but that could change if the code is modified in the
future. To avoid any potentially issue due to this consistently use
non-blocking assignments.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-24 15:27:22 +01:00
Lars-Peter Clausen 3339f68926 axi_dmac: axi_dmac_hw.tcl: Set read and write issuing capabilities
The axi_dmac can issue up to FIFO_SIZE read and write requests in parallel.
This is done in order to maximize throughput and compensate for for
latency.

Set the {read,write}IssuingCapability properties accordingly on the AXI
master interfaces. Otherwise qsys might decide to insert bridges that
artificially limit the number of requests, which in turn might affect
performance.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-24 15:27:02 +01:00
Lars-Peter Clausen 6f36d013d3 axi_dmac: axi_dmac_hw.tcl: Set default DMA_LENGTH_WIDTH to 24
This matches the default parameter of the HDL code.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-24 15:26:17 +01:00
Lars-Peter Clausen 374c49ff48 axi_dmac: axi_dmac_hw.tcl: Automatically detect clock domains
Qsys allows to query to query the clock domain that is associated with a
clock input of a peripheral. This allows to automatically detect whether
the different clocks of the DMAC are asynchronous and CDC logic needs to be
inserted or not.

Auto-detection has the advantages that the configuration parameters don't
need to be set manually and the optional configuration will be choose
automatically. There is also less chance of error of leaving the settings
in a wrong configuration when e.g. the clock domains change.

In case the auto-detection should ever fail configuration options that
provide a manual overwrite are added as well.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-24 16:06:37 +02:00
Lars-Peter Clausen 4f009620b5 axi_dmac: axi_dmac_hw.tcl: Cleanup configuration parameters
Group configuration parameters by function, provide human readable labels
as well as specify the allowed ranges for each parameter.

This prevents accidental misconfiguration and also makes it easier to
inspect (or change) the configuration in the Qsys GUI.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-24 16:06:37 +02:00
Lars-Peter Clausen 63f280676a avl_adxcfg: Consistently use non-blocking assignments
In this particular case the behaviour is the same with non-blocking and
blocking assignments, but that could change if the code is modified in the
future. To avoid any potentially issue due to this consistently use
non-blocking assignments.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-24 16:06:00 +02:00
Lars-Peter Clausen bd8d676346 library: Use ad_ip_intf_s_axi were applicable
Use the ad_ip_intf_s_axi helper function to create the axi4lite slave
interface for memory mapped peripherals. This slightly reduces the amount
of boilerplate code in the peripheral's *hw.tcl

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-24 15:52:37 +02:00
Lars-Peter Clausen 7a04b4723b adi_ip_alt.tcl: ad_ip_intf_s_axi: Allow to specify AXI interface address width
The address width of the AXI interface depends on the size of the register
and can differ from peripheral to peripheral. Add a parameter to the
function that allows to specify the address width, this allows to use the
function for more peripherals.

Keep the current value of 16 bits as the default if the parameter is not
specified.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-24 15:21:52 +02:00
Lars-Peter Clausen e1e0406a49 altera: axi_adxcvr: Reduce register map interface address width
The axi_adxcvr register map only uses a single 4k page, make this explicit.

This will allow for tighter packaging in the limited available total
register map space.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-24 15:21:52 +02:00
Rejeesh Kutty bc4526cc8a axi_ad9361/altera- add 10 support 2017-07-21 10:33:44 -04:00
Rejeesh Kutty 9b26763e3b ad9361/xilinx- missing up_rstn 2017-07-21 09:08:28 -04:00
Lars-Peter Clausen c1d6ee8f1b Partially revert "hdlmake.pl - updates"
This partially reverts commit a8ade15173.

Remove the nonsensical Makefile dependencies that got added by accident.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-21 15:06:22 +02:00
Adrian Costina afbce10ab9 axi_dac_interpolate: Added matlab file for interpolation filters 2017-07-21 14:37:27 +03:00
Adrian Costina bf810bcc4b axi_adc_decimate: Added matlab file for filters 2017-07-21 14:36:27 +03:00
Rejeesh Kutty a8ade15173 hdlmake.pl - updates 2017-07-20 15:11:21 -04:00
Rejeesh Kutty d132ed45cd arradio- timing violations fix 2017-07-20 15:08:21 -04:00
Rejeesh Kutty 36a9ea40b1 altera- remove lvds/serdes/cmos cores 2017-07-20 14:19:40 -04:00
Rejeesh Kutty e1c95b23ea alt_serdes- remove c5 support 2017-07-20 14:16:32 -04:00
Rejeesh Kutty a27b30d380 library- remove c5 cores 2017-07-20 14:12:00 -04:00
Rejeesh Kutty 6c986d9b6a hdl/library- fix syntax errors/synthesis warnings 2017-07-20 14:07:32 -04:00
Lars-Peter Clausen 4f5f15e36e up_clock_mon: Explicitly truncate d_count during up_d_count assignment
The MSB of the d_count signal is used as a overflow marker to stop the
counter from incrementing in the monitored clock domain. It is not exported
through the register map and truncated when assigned to the up_d_count
signal.

Make the truncation explicit to make it clear that this is not a mistake
and to avoid warnings about implicit truncation.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 19:45:27 +02:00
Lars-Peter Clausen 634340c170 jesd204: jesd204_up_common: Rename clock monitor instance to i_clock_mon
The generic Altera clock monitor constraints expect the instance to be
called i_clock_mon. Adjust the code accordingly.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 19:45:26 +02:00
Lars-Peter Clausen 4e8327efd2 jesd204: jesd204_up_ilas_mem: Fix blocking assignment
In this particular case the behaviour is the same with non-blocking and
blocking assignments, but that could change if the code is modified in the
future. To avoid any potentially issue due to this consistently use
non-blocking assignments.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 19:45:26 +02:00
Lars-Peter Clausen cc27c5e00c axi_dmac: axi_dmac_hw.tcl: Set read and write issuing capabilities
The axi_dmac can issue up to FIFO_SIZE read and write requests in parallel.
This is done in order to maximize throughput and compensate for for
latency.

Set the {read,write}IssuingCapability properties accordingly on the AXI
master interfaces. Otherwise qsys might decide to insert bridges that
artificially limit the number of requests, which in turn might affect
performance.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 19:45:26 +02:00
Lars-Peter Clausen 62a06f6958 axi_dmac: axi_dmac_hw.tcl: Set default DMA_LENGTH_WIDTH to 24
This matches the default parameter of the HDL code.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 19:45:26 +02:00
Rejeesh Kutty a63e268d6e arradio/c5soc- interface updates 2017-07-20 13:05:07 -04:00
Rejeesh Kutty fca88caf93 arradio/c5soc- interface updates 2017-07-20 13:05:07 -04:00
Lars-Peter Clausen 369fe69d34 jesd204: tx_ctrl: Fix status_sync assignment
The SYNC signal that gets reported through the status interface should be
the output (second stage) of the synchronizer circuit.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-17 17:13:02 +02:00
Lars-Peter Clausen 1f2e189ff2 jesd204: jesd204_up_sysref: Remove unused signals
These signals are leftovers of an earlier implementation version, remove
them.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-17 17:13:02 +02:00
Lars-Peter Clausen a9fe0fa530 jesd204: jesd204_up_common: Add missing core_cfg_transfer_en declaration
Make sure the core_cfg_transfer_en signal is declared before they are used.
Strictly speaking the current code is correct and synthesis correctly, but
declaring the signals make the intentions of the code more explicit.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-17 17:13:02 +02:00
Lars-Peter Clausen d164209355 jesd204: axi_jesd204_up_rx_lane: Fix padding signal width
The upper padding zeros should be 26 bits wide.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-17 17:13:02 +02:00
Lars-Peter Clausen fa46688be5 jesd204: Add names for generate for-blocks
Be more standard compliant and assign names to generate for-blocks. This is
required for Altera/Intel support.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-17 17:13:02 +02:00
Lars-Peter Clausen cdf005ab83 axi_dmac: request_arb: Add missing req_gen_{valid,ready} signal declaration
Make sure the req_gen_valid and req_gen_ready signals are declared before
they are used. Strictly speaking the current code is correct and synthesis
correctly, but declaring the signals make the intentions of the code more
explicit.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-17 17:13:02 +02:00
Istvan Csomortani 2d9b3491c6 axi_dmac: Update to verilog-2001 coding style
Fix all the non standard parameter declarations in all verilog files.
2017-07-15 09:25:14 +01:00
Istvan Csomortani 4832bc1a0c axi_dacfifo: Fix port width at axi_dacfifo_wr 2017-07-14 16:47:34 +03:00
Istvan Csomortani 4ea6b0d6d8 jesd204: Update constraints for tx register map
In some cases, the 'core_ilas_config_data' registers will be infered as
FDRE, instead of FDSE. Therefor a max delay definition, which are using
the S pin as its endpoint, it can become invalid, nonexistent.
Generalize the path, using the register itself as endpoint.
2017-07-10 13:38:31 +01:00
Istvan Csomortani 00944ecfd9 axi_xcvrlb: Fix util_adxcvr_xch instantiation (6d4430) 2017-07-06 13:08:29 +01:00
Istvan Csomortani a9543bdf2c axi_dacfifo: Fix axi_dlast generation
The axi_dlast should be asserted max one data beat cycle.
2017-07-06 10:30:41 +01:00
Istvan Csomortani 2ac096cc3b axi_dacfifo: Few cosmetic changes
The width of the constant, which going to be assigned to a register,
has to be equal with the width of the register.
2017-07-06 10:29:05 +01:00
Istvan Csomortani 75a18da971 axi_dacfifo: Increase the width of axi_last_beats and wvalid_counter
Increase the width of wvalid_counter, should be equal with awlen width.
The wvalid_counter needs to count from zero to the required burst
length. The maximum burst length is 255, so the width of the counter
have to be 8 bits. axi_last_beats will get the last axi burst length.
2017-07-06 10:24:36 +01:00
Istvan Csomortani baec8a0777 axi_dacfifo: Define DMA/DAC_MEM_ADDRESS as parameter
Make the depth of the internal CDC memories parameterizable.
2017-07-06 10:11:50 +01:00
Istvan Csomortani 7340d8aa16 axi_dacfifo: DAC side CDC fifo control update
The fifo will ask for a new data from the DDR, if the current
level is lower than the high threshold. This will prevent overflow.
By deleting the lower threshold, we can avoid ocassional underflows,
when the DAC rate is closer to the max DDRx rate.
2017-07-06 10:01:27 +01:00
Istvan Csomortani a0b33898d2 axi_dacfifo: Add gray coder/decoder module
Use gray coder/decoder modules, instead of functions.
This way it can be used paramterized data width on the
coders/decoders.
2017-07-06 10:01:27 +01:00
Istvan Csomortani 866d79dee2 ad_axis_inf_rx: Delete redundant local paramter
All verilog file are using the Verilog-2001 standard to define
and/or declare ports. Definin a port width with a local parameter
is a bad practive, when this standard is used. Some simulators
will crash. Try to avoid it.
2017-07-06 10:01:27 +01:00
Istvan Csomortani cfa22f36bc axi_dacfifo: Fix the dma_ready signal generation
Fix the dma_ready mux in top module, and the dma_ready_out reset
logic in axi_dacfifo_wr module. Also, both write and read addresses
of the async CDC fifo (inside the axi_dacfifo_wr) should be reset
before a dma transaction starts.
2017-07-06 10:01:17 +01:00
Adrian Costina 9f8a94df69 axi_logic_analyzer: Streaming flag initial commit
If the streaming bit is set, after the trigger condition is met
data will be continuosly captured by the DMA. The streaming bit
must be set to 0 to reset triggering.
2017-07-03 18:00:23 +03:00
Adrian Costina 99e8aa385a axi_adc_trigger Streaming flag initial commit
If the streaming bit is set, after the trigger condition is met,
data will be continuosly captured by the DMA. The streaming bit
must be set to 0 to reset triggering.
2017-07-03 16:54:40 +03:00
Adrian Costina b4467ff4dc axi_adc_trigger: Fix triggered flag 2017-07-03 13:00:51 +03:00
Adrian Costina 291718d6a8 axi_logic_analyzer: Fixed triggered flag 2017-07-03 12:59:24 +03:00
Lars-Peter Clausen 8755e6da44 axi_logic_analyzer: Fix direction change in non-streaming mode
In non-streaming mode we want direction changes to be applied immediately.
The current code has a typo and checks the wrong signal. overwrite_data
holds the configured output value of the pin, whereas overwrite_enable
configures whether the pin is in streaming or manual mode.

For correct operation the later signal should be used to decide whether a
direction change should be applied. Otherwise the direction change will
only be applied if the output value of the pin is set to logic high.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-29 13:16:48 +02:00
Lars-Peter Clausen 121e04e94e util_adxcvr: Bring back channel 8
This was accidentally deleted in commit 6d4430cfda
("axi_adxcvr/util_adxcvr: Fix non-broadcast DRP access").

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-29 13:16:48 +02:00
Lars-Peter Clausen 6d4430cfda axi_adxcvr/util_adxcvr: Fix non-broadcast DRP access
When using non-broadcast access to the GT DRP registers lane filtering is
done on both sides. The ready and data signals are filtered in the in the
axi_adxcvr module and the enable signal is filtered in the util_adxcvr
module. This works fine as long as both sides use the same transceiver IDs.
E.g. channel 0 of the axi_adxcvr module is connected to channel 0 of the
util_adxcvr module.

But this is not always the case. E.g. on the ADRV9371 platform there are
two RX axi_adxcvr modules (RX and RX_OS) connected to the same util_adxcvr.
The first axi_adxcvr uses lane 0 and 1 of the util_adxcvr, the second uses
lane 2 and 3.

Non-broadcast access for the first RX axi_adxcvr module works fine, but
always generates a timeout for the second axi_adxcvr module. This is
because lane 0/1 of the axi_adxcvr module is connected to lane 2/3 of the
util_adxcvr and when ID based filtering is done both can't match at the
same time.

To avoid this perform the filtering for all the signals in the axi_adxcvr
module. This makes sure that the same base ID is used.

This also removes the sel signal from the transceiver interfaces since it
is no longer used on the util_adxcvr side.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-28 17:30:51 +02:00
Istvan Csomortani e4e74fe6ce common: Delete deprecated modules 2017-06-26 16:12:34 +01:00
Istvan Csomortani 6ebef5dde0 make: Update make files 2017-06-26 15:51:19 +01:00
Istvan Csomortani f00bf926ca axi_ad9652: Remove deprecated IP 2017-06-26 15:46:46 +01:00
Istvan Csomortani 68a50317e9 axi_ad9643: Remove deprecated IP 2017-06-26 15:46:33 +01:00
Istvan Csomortani 9363ee0316 axi_ad9234: Remove deprecated IP 2017-06-26 15:46:12 +01:00
Istvan Csomortani 6bcb327d5f common: Remove deprecated modules 2017-06-26 15:43:57 +01:00
Istvan Csomortani 95877fc5ce util_ccat: Remove deprecated IP 2017-06-26 15:43:10 +01:00
Adrian Costina a5bb72cbba axi_logic_analyzer: Added triggered flag 2017-06-23 14:37:23 +03:00
Adrian Costina 9d572b406b axi_adc_trigger: added triggered flag 2017-06-23 14:36:22 +03:00
Rejeesh Kutty 354b311f3d library/avl_adxcvr: fpll fixes 2017-06-21 15:26:00 -04:00
Lars-Peter Clausen 94586a5b49 jesd204: tb: Fix signal width mismatch warnings
Always explicitly specify the signal width for constants to avoid warnings
about signal width mismatch.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
Lars-Peter Clausen 885b364a46 jesd204: rx_static_config: Set RBD to 0
The buffer delay should be 0 in the default configuration. The current
value of 0xb must have slipped in by accident.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
Lars-Peter Clausen 71cc052825 jesd204: rx: Use standalone counter for lane latency monitor
Use a single standalone counter that counts the number of beats since the
release of the SYNC~ signal, rather than re-using the LMFC counter plus a
dedicated multi-frame counter.

This is slightly simpler in terms of logic and also easier for software to
interpret the data.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
Lars-Peter Clausen 9e50f5afa8 jesd204: Handle sysref events in the register map
There are currently two sysref related events. One the sysref captured
event which is generated when an external sysref edge has been observed.
The other is the sysref alignment error event which is generated when a
sysref edge is observed that has a different alignment from previously
observed sysref edges.

Capture those events in the register map. This is useful for error
diagnostic. The events are sticky and write-1-to-clear.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
Lars-Peter Clausen d3b44906c3 jesd204: Properly align LMFC offset in register map
The internal LMFC offset signals are in beats, whereas the register map is
in octets. Add the proper alignment padding to the register map to
translate between the two.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
Lars-Peter Clausen baa256e34c jesd204: Slightly rework sysref handling
For SYSREF handling there are now three possible modes.

1) Disabled. In this mode the LMFC is generated internally and all external
SYSREF edges are ignored. This mode should be used for subclass 0 when no
external sysref is available.
2) Continuous SYSREF. An external SYSREF signal is required and the LMFC is
aligned to the SYSREF signal. The SYSREF signal is continuously monitored
and if a edge unaligned to the previous edges is detected the LMFC is
re-aligned to the new edge.
3) Oneshot SYSREF. Oneshot SYSREF mode is similar to continuous SYSREF mode
except only the first edge is captured and all further edges are ignored,
re-alignment will not happen.

Both in continuous and oneshot signal at least one external sysref edge is
required before an LMFC is generated. All events that require an LMFC will
be delayed until a SYSREF edge has been captured. This is done to avoid
accidental re-alignment.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
Lars-Peter Clausen bf88527119 library: jesd204: jesd204_up_common: Fix indention
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
Lars-Peter Clausen 9f954303ac up_clock_mon: Fix stopped clock detection logic
A broken version of the stopped clock detection logic was merged by
accident. Fix it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
Istvan Csomortani f415b4f973 axi_ad5766: Delete unused interface definition 2017-06-20 11:55:10 +01:00
Adrian Costina 871855c9ec axi_logic_analyzer: Fix delayed trigger assertion condition 2017-06-19 10:58:22 +03:00
Matthew Fornero d840baee28 util_clkdiv: Register output port as a clock (#33)
If the output pin is not defined as a clock, some of the Vivado IPI
propagation TCL will error out.

Signed-off-by: Matt Fornero <matt.fornero@mathworks.com>
2017-06-19 07:52:43 +01:00
Rejeesh Kutty dc94dd3ea7 jesd204- apply constraints after top 2017-06-16 15:30:18 -04:00
Rejeesh Kutty 513f6ae18a adi_ip.tcl- general rule- order independent constraints 2017-06-16 13:51:35 -04:00
Rejeesh Kutty 9e2d55ed07 adi_ip_alt: allow composition only parameter settings 2017-06-15 11:36:39 -04:00
Rejeesh Kutty 9464f342cf avl_adxcvr: remove arria v support 2017-06-15 11:36:14 -04:00
Adrian Costina 2fc5d08c0b axi_gpreg: Fixed constraints 2017-06-13 14:04:43 +03:00
Rejeesh Kutty 173837f5b2 altera- altera ip interfaces has no consistency 2017-06-09 16:21:44 -04:00
Rejeesh Kutty 227bd3edfe alt_ifconv-- qsys workaround 2017-06-09 16:17:34 -04:00
Rejeesh Kutty 034aa7c1ee altera 16.1- recommends using fpll for dedicated low skew clock routing 2017-06-08 10:50:52 -04:00
Adrian Costina 3f2c885189 axi_logic_analyzer: Update triggering delay mechanism 2017-06-08 12:01:49 +03:00
Adrian Costina 256a685004 axi_adc_trigger: Update triggering delay mechanism 2017-06-08 12:00:27 +03:00
Istvan Csomortani 7554887982 avl_dacfifo: Fix timing violation
+ Transfer avl_last_beats into dac clock domain
 + Update constraint file
2017-06-07 11:02:44 +01:00
Rejeesh Kutty dd48929327 hdlmake.pl - updates 2017-06-06 12:25:35 -04:00
Rejeesh Kutty 41d305b6b6 up_clock_mon- name changes 2017-06-06 11:36:18 -04:00
AndreiGrozav 4cc5052b3a util_fir_int: Fix valid assignment 2017-06-06 17:53:41 +03:00
Adrian Costina ac55e850a9 axi_logic_analyzer: Added trigger delay register, renamed fifo depth register 2017-06-06 15:37:00 +03:00
Adrian Costina 3148c85f73 axi_adc_trigger: Added trigger delay register, renamed fifo depth register 2017-06-06 15:35:59 +03:00
Rejeesh Kutty 95c446a41d adi_ip- initialize xdc list when ip is created 2017-06-01 15:49:18 -04:00
Rejeesh Kutty 6a437472f2 jesd204-sub-ip- no top files 2017-06-01 15:48:48 -04:00
Istvan Csomortani 50cdb6db67 Merge branch 'jesd204' into dev 2017-05-31 20:44:32 +03:00
Istvan Csomortani cb4e8f66ef axi_ad9963: Delete unused source from *_ip.tcl 2017-05-31 18:27:47 +03:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Adrian Costina 3a4a91b6f1 util_extract: Estetic changes 2017-05-31 11:27:32 +03:00
Adrian Costina 7aa1673238 util_extract: Update parameter names 2017-05-29 16:04:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Rejeesh Kutty aaae350b3d alt_serdes- 16.1 updates 2017-05-26 11:00:07 -04:00
Rejeesh Kutty 25e42c49d6 library: move alt cores to common 2017-05-26 10:51:25 -04:00
Rejeesh Kutty ff037c0286 altera 16.1 ip changes 2017-05-26 10:48:00 -04:00
Rejeesh Kutty 097924b95d altera 16.1 ip changes 2017-05-26 10:46:28 -04:00
Istvan Csomortani 10898d6618 constraints: Split the regmap CDC constraint into separate file 2017-05-25 15:12:16 +03:00
Istvan Csomortani cb8d6830f5 avl_dacfifo: Update constraints 2017-05-25 15:12:16 +03:00
Istvan Csomortani 3ee7ed7375 avl_dacfifo: Cosmetic changes 2017-05-25 15:12:15 +03:00
Istvan Csomortani 154e936a4b avl_dacfifo: Fix issues with avl_dacfifo_wr
+ fix issues with the last partial avalon transfer.
 + fix reset related problems
2017-05-25 15:12:15 +03:00
Istvan Csomortani e34e87e7f8 avl_dacfifo: Add support for partial avalon transfers
By adding support for partial avalon transfers (data width < bus width),
valid data set size (DMA transfer length) will be dependent on the DMA bus
width only.
2017-05-25 15:12:15 +03:00
Istvan Csomortani a993eefe57 avl_dacfifo: Grey coder/decoder integration 2017-05-25 15:12:14 +03:00
Istvan Csomortani 0bf6a37bd0 common: Add grey coder and decoder modules 2017-05-25 15:12:14 +03:00
Istvan Csomortani 14a058195d avl_dacfifo: Add avl_dacfifo_byteenable_coder
Define and integrate avl_dacfifo_byteenabke_coder module,
which generates the byteenable signal for the avalon interface.
2017-05-25 15:12:14 +03:00
Istvan Csomortani 81fa65cd51 avl_dacfifo: Few cosmetic changes on avl_dacfifo_wr
+ avl_write_transfer_done_s is a redundant net
 + specify the net state explicitly on if statements
 + to define the edge of avl_mem_fetch_wr_address signal,
its register and its second sync register should be used
2017-05-25 15:12:13 +03:00
Istvan Csomortani 398619d866 avl_dacfifo: Add support for MEM_RATIO 32 2017-05-25 15:12:13 +03:00
Istvan Csomortani a1539a62b7 avl_dacfifo: Integrate util_delay into dac_xfer_out path
The ad_mem_asym memory read interface has a 3 clock cycle delay, from the
moment of the address change until a valid data arrives on the bus;
because the dac_xfer_out is going to validate the outgoing samples (in conjunction
with the DAC VALID, which is free a running signal), this module will compensate
this delay, to prevent duplicated samples in the beginning of the
transaction.
2017-05-25 15:12:13 +03:00
Istvan Csomortani 6d52034abb avl_dacfifo: dma_ready was muxed incorrectly 2017-05-25 15:12:12 +03:00
Istvan Csomortani da68705fee avl_dacfifo: Fix the avalon address switch 2017-05-25 15:12:12 +03:00
Istvan Csomortani 04f397f688 avl_dacfifo: Fix a few control signals
+ avl_last_transfer depends on the avl_xfer_req state
  + avl_xfer_req will be asserted after the last avalon write
transfer
2017-05-25 15:12:12 +03:00
Istvan Csomortani 8f9cadb017 avl_dacfifo: Fix the avl_write generation
The asymetric memory has a 3 clock cycle delay on its read
interface, therefor the minimum distance between two consecutive
avalon write should be 3.
2017-05-25 15:12:11 +03:00
Istvan Csomortani 0f1e51ac98 avl_dacfifo: Fix alv_mem_readen generation 2017-05-25 15:12:11 +03:00
Istvan Csomortani f456ebc6f0 avl_dacfifo: Few cosmetic changes on avl_dacfifo_wr
+ all net names should have a *_s postfix
  + avl_burstcount is a constant 1, no need for an additional
register for it
  + all CDC should have two synchronization register, add
avl_last_beat_req_m2
2017-05-25 15:12:11 +03:00
Istvan Csomortani 6ea87d094e util_delay: Initial commit
Generic module to introduce a fix N cycle delay into a datapath.
2017-05-25 15:12:10 +03:00
Istvan Csomortani 9a6dc36289 avl_dacfifo: Fix indentation for acl_dacfifo.v 2017-05-25 15:12:10 +03:00
Istvan Csomortani 7666c9f0d2 avl_dacfifo: Add a parameter AVL_ADDRESS_WIDTH 2017-05-25 15:12:10 +03:00
Istvan Csomortani 6dbbe2f1ca altera/ad_mem_asym: Fix grounded bus for marco instance
The "'b0" constant will be translate as a 32 bit width vector by
ModelSim, and will throw a buswidth mismatch error. Tie the data_b
bus to zero, using its width parameter.
2017-05-25 15:12:09 +03:00
Lars-Peter Clausen d883aabcc1 adi_ip.tcl: Use analog.com for interface vendor
Currently the scripts use 'analog.com' as the vendor property for IP cores,
but 'ADI' for interfaces.

Make things consistent by using 'analog.com' for both interfaces as well
as IP cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-24 18:10:15 +02:00
Lars-Peter Clausen 7020f94968 interfaces: Add dependencies to rule
Make sure that the XML files are re-build when any of the scripts that are
used to generated it are modified.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-24 18:10:15 +02:00
Lars-Peter Clausen 5ba1c4fef3 interfaces: Simplify Makefile
All the rules to generate the XML files are the same. Reduce the number of
rules by useing wildcard matching for the rule target.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-24 18:09:52 +02:00
Adrian Costina 229829e4dc axi_ad9963: Add scale only correction option 2017-05-24 15:55:45 +03:00
Adrian Costina c7df3e8ae9 ad_iqcor: Add scale only correction option 2017-05-24 15:54:58 +03:00
Lars-Peter Clausen 1202286c3d Add ADI JESD204 link layer cores
The ADI JESD204 link layer cores are a implementation of the JESD204 link
layer. They are responsible for handling the control signals (like SYNC and
SYSREF) and controlling the link state machine as well as performing
per-lane (de-)scrambling and character replacement.

Architecturally the cores are separated into two components.

1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take
care of the JESD204 protocol handling. They have configuration and status
ports that allows to configure their behaviour and monitor the current
state. The processing cores run entirely in the lane_rate/40 clock domain.

They have a upstream and a downstream port that accept and generate raw PHY
level data and transport level payload data (which is which depends on the
direction of the core).

2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The
configuration interface cores provide a register map interface that allow
access to the to the configuration and status interfaces of the processing
cores. The configuration cores are responsible for implementing the clock
domain crossing between the lane_rate/40 and register map clock domain.

These new cores are compatible to all ADI converter products using the
JESD204 interface.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Lars-Peter Clausen aba62d96c9 util_cdc: Add multi-bit data synchronization module
The sync_data module can be used to continuously transfer multi-bit signals
like status signals safely from the source to the destination clock
domain. A transfer takes 2 source and 2 destination clock cycles. It is not
guaranteed that all transitions on the source side will be visible on the
target side if the signal is changing faster than this. Logic using this
block should be aware of it. The primary intention is for it to be used for
slowly changing status signals.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Lars-Peter Clausen ab381825da util_cdc: Add event synchronizer
The event synchronizer can be used to safely transfer 1-bit 1-clock cycle
event signals from one clock domain to another.

For each event recorded in the source domain it is guaranteed that a event
will be generated in the target domain at a later point in time. It is
possible though that multiple events in the source domain will be coalesced
into a single event in the target domain if events are generated faster
than they can be transferred.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Lars-Peter Clausen 01aea161fa Create CDC helper library
Move the CDC helper modules to a dedicated helper modules. This makes it
possible to reference them without having to use file paths that go outside
of the referencing project's directory.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Lars-Peter Clausen ed23eb950e adi_ip.pl: adi_ip_properties_lite: Set core name to the specified name
Currently the name of the newly created IP core is automatically inferred
from the top-level module. This works fine if there is only one top-level
IP. But for an IP core that is a collection of helper modules this fails.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Lars-Peter Clausen 19636e8c55 adi_ip.tcl: adi_add_bus_clock: Set polarity depending on the reset name suffix
Currently the polarity of the reset signal is always set to negative.
Change this so that the polarity is selected on the suffix of the name. If
it ends with a 'n' or 'N' the polarity will be negative, otherwise it will
be positive.

This allows this function to be used with reset signals that have positive
polarity.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Lars-Peter Clausen 341a695163 adi_ip.pl: Add support for creating multi busses
This patch adds a helper function that allows to create multiple ports for
a single set of underlying signals. This is useful when the number of ports
is a configuration parameter. It sort of allows the emulation of port
arrays without having to have on set of input/output signals for each port,
instead the signals are shared by all ports.

The following snippet illustrates how this can for example be used to
generate multiple AXI-Streaming ports from a single set of signals.

<verilog>
	module #(
		parameter NUM_PORTS = 2
	) (
		input [NUM_PORTS*32-1:0] data,
		input [NUM_PORTS-1:0] valid,
		output [NUM_PORTS-1:0] ready,
	);
	...
	endmodule
</verilog>

<tcl>
	adi_add_multi_bus 8 "data" "slave" \
		"xilinx.com:interface:axis_rtl:1.0" \
		"xilinx.com:interface:axis:1.0" \
		[list \
			{ "data" "TDATA" 32} \
			{ "valid" "TVALID" 1} \
			{ "ready" "TREADY" 1} \
	  ] \
	  "NUM_PORTS > {i})"
</tcl>

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Lars-Peter Clausen e4a4a7a1b8 adi_ip.tcl: Set processing order of IP core constraint files back to late
Commit 2f023437b4 ("adi_ip- remove adi_ip_constraints") changed the
default processing order of IP core constraint files from late to normal.

This is problematic because some IP core constraint files try to access
clocks that are that are generated by different files with the normal
processing order level. These clock may or may not be available to the IP
core constraint file depending on the (random) order in which the files
were processed.

To avoid this issue change the default processing order back to late.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Lars-Peter Clausen 55cc5515ad adi_ip.tcl: Use analog.com for interface vendor
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Lars-Peter Clausen 3d8e05ac17 up_clock_mon: Make counter width configurable
The clock monitor reports the ratio of the clock frequencies of a known
reference clock and a monitored unknown clock. The frequency ratio is
reported in a 16.16 fixed-point format.

This means that it is possible to detect clocks that are 65535 times faster
than the reference clock. For a reference clock of 100 MHz that is 6.5 THz
and even if the reference clock is running at only 1 MHz it is still 65
GHz, a clock rate much faster than what we'd ever expect in a FPGA.

Add a configuration option to the clock monitor that allows to reduce the
number of integer bits of ratio. This allows to reduce the utilization
while still being able to cover all realistic clock frequencies.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Lars-Peter Clausen 1ecc5aaffc up_clock_mon: Detect stopped clock
Currently when the monitored clock stops the clock monitor retains the old
frequency ratio value and there is no way to detect that the clock has
stopped and the reported value is indistinguishable form a clock still
running at the right rate.

If a full iteration as elapsed on the monitoring side and there is no
indication that the counter on the monitored side has started running set
the reported clock ratio value to 0 to indicate that the clock has stopped.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Lars-Peter Clausen 139876d28a up_clock_mon: Remove extra hold register
Currently the clock monitor features a hold register in the monitored clock
domain. This old register is used to store a instantaneous copy of the
counter register. The value in the old register is then transferred to the
monitoring domain. Since the counter is continuously counting it is not
possible to directly transfer it since that might result in inconsistent
data.

Instead stop the counter and hold the registers stable for a duration that
is long enough for the monitoring domain to correctly capture the value.
Once the value has been transferred the counter is reset and restarted for
the next iteration.

This allows to eliminate the hold register, which slightly reduces
utilization.

The externally visible behaviour is identical before and after the patch.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Lars-Peter Clausen 696305360c interfaces: Add dependencies to rule
Make sure that the XML files are re-build when any of the scripts that are
used to generated it are modified.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Lars-Peter Clausen a44420fa8f interfaces: Simplify Makefile
All the rules to generate the XML files are the same. Reduce the number of
rules by useing wildcard matching for the rule target.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Rejeesh Kutty 0930c486d2 axi_hdmi_rx- move data to an iob 2017-05-19 16:25:54 -04:00
Lars-Peter Clausen 858065d49b library: Sort Makefile
Sort the entries in the library Makefile alphabetical. Keeping it ordered
makes it easier to track changes compared to randomly reshuffling it
every time a new entry is added.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-19 15:33:26 +02:00
Rejeesh Kutty 393577c911 util_adxcvr- 2016.4 gthe4 updates 2017-05-18 14:49:18 -04:00
Rejeesh Kutty 80a3f45b9f alt_mul- qsys replacement 2017-05-18 10:38:48 -04:00
Rejeesh Kutty 598bd7e226 resolving conflicts 2017-05-17 16:18:53 -04:00
Rejeesh Kutty 6649b23bc8 alt-mem-asym - replace mega function cores 2017-05-17 16:13:26 -04:00
Rejeesh Kutty 828c2406cb adi-ip-alt allow changing device family 2017-05-17 16:13:26 -04:00
Rejeesh Kutty bea72232a3 alt_mem_asym- qsys component 2017-05-17 16:13:26 -04:00
Istvan Csomortani fe140a054f license: Fix VHDL license header 2017-05-17 18:28:06 +03:00
AndreiGrozav 70e3dd00ff scripts: Update required tool versions 2017-05-17 16:45:20 +03:00
Lars-Peter Clausen bf44f357fe Fix VHDL files license header, second try
While VHDL uses -- for comments uris still use //.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 15:25:08 +02:00
Lars-Peter Clausen 5ee9480142 Fix VHDL files license header
VHDL uses '--' for comments rather than '//'.

Also remove left over old license headers.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 15:21:06 +02:00
AndreiGrozav 18bc5465df axi_usb_fx3: Add missing ports 2017-05-17 14:48:28 +03:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
AndreiGrozav 857ad45d57 util_fir_int: Force 1/8 filter input data rate 2017-05-16 19:35:24 +03:00
AndreiGrozav 3f5d930cde axi_adc_decimate/cic_decim: Fix clk_enable warning
- fix clk_enable zero replication warning
2017-05-16 19:35:24 +03:00
AndreiGrozav fd7db4fcf3 util_tdd_sync: add missing ports 2017-05-16 19:35:24 +03:00
AndreiGrozav cf3737122b Remove duplicare wire declaration
-Introduced by updating to verilog-2001
2017-05-16 19:35:24 +03:00
AndreiGrozav 41e25e7c96 Add missing ad_serdes_out interface ports 2017-05-16 19:35:24 +03:00
Adrian Costina 0c5dabe358 axi_ad9963: Update constraints as adc_common and dac_common paths have been renamed 2017-05-15 18:59:09 +03:00
Adrian Costina ce4f9bf906 up_dac_common: rename internal signals 2017-05-15 18:58:26 +03:00
Rejeesh Kutty ebeebdddf0 altera- infer latest versions 2017-05-12 13:40:14 -04:00
Rejeesh Kutty c728299e71 altera- default to latest version 2017-05-12 13:25:17 -04:00
Rejeesh Kutty ecfa15bfce version check- change to critical warning 2017-05-12 09:51:48 -04:00
AndreiGrozav e4ae391237 axi adc cores: Add missing ports to up_adc_common instance 2017-05-12 13:39:05 +03:00
AndreiGrozav 0e1e507541 axi dac cores: Add missing ports to up_dac_common instance 2017-05-12 13:37:34 +03:00
Rejeesh Kutty d93a6d062e fmcadc5-sync: added a convenience timer 2017-05-11 12:39:39 -04:00
Istvan Csomortani 8e7b577c94 axi_ad5766: Add missing ports to up_dac_common instance 2017-05-11 17:25:31 +03:00
Istvan Csomortani 6e5d965211 axi_ad5766: sdo_mem size is 3 2017-05-11 17:25:31 +03:00
Istvan Csomortani 7968ca64a6 axi_ad5766: Delete redundant parameters 2017-05-11 17:25:31 +03:00
Istvan Csomortani e327166cf2 axi_generic_adc: Update port names for up_adc_common instance 2017-05-11 11:00:24 +03:00
Rejeesh Kutty 039ae9ae92 fmcadc5- syntax/port name fixes 2017-05-10 16:30:15 -04:00
Rejeesh Kutty fea6eb68be up_adc_common- port name changes 2017-05-10 14:45:17 -04:00
Rejeesh Kutty c2dd991736 axi_fmcadc5- sign-extend and interleave (core is too late) 2017-05-10 14:33:56 -04:00
Rejeesh Kutty 78435ebbb7 ad9625- add an option to control cs monitoring 2017-05-10 14:33:56 -04:00
Rejeesh Kutty d374f5b091 library/up_adc_common- add sref sync option 2017-05-10 14:33:56 -04:00
Rejeesh Kutty 61bbfb2c82 library/axi_fmcadc5_sync- remove dependecy on adc-core (driver shows up late) 2017-05-10 14:33:56 -04:00
AndreiGrozav c44de7021a axi_ad9739a: Fix DDS set frequency
- DDS out frequency was 4 times greater than the desired frequency
2017-05-10 17:39:00 +03:00
Istvan Csomortani 5fe008d887 axi_ad9371: Update dac_clk_ratio to 2
DAC sampling frequency is two times of the JESD204
core clock.
2017-05-10 11:12:45 +03:00
Rejeesh Kutty b6e9c92f46 axi_fmcadc5_sync- raw inputs & constraint fixes 2017-05-08 10:29:06 -04:00
Rejeesh Kutty 391a14be7a hdlmake.pl updates 2017-05-04 13:59:47 -04:00
Rejeesh Kutty 1bd444b47f axi_fmcadc5_sync- calcor added 2017-05-04 13:58:35 -04:00
AndreiGrozav f93a003ed1 axi_ad9434: Fix input data rate 2017-05-04 16:43:09 +03:00
Istvan Csomortani 6387b53266 ad77681evb: Initial commit 2017-05-04 12:19:11 +03:00
Istvan Csomortani 3ba57582bb spi_engine_offload: Add a CDC module for trigger reception
There are devices which have a asynchronous data ready signal. (asynchronous
with the spi clock) The CDC stages can be enabled by setting up
the ASYNC_TRIG parameter.
2017-05-04 12:14:06 +03:00
Istvan Csomortani 07956cfe66 spi_engine: Define parameter inside the module statement
Part of the effort to update all verilog files to use the
ANSI-C style port list in module definitions. (verilog-2001)
2017-05-04 12:13:47 +03:00
Rejeesh Kutty d29f420ffa axi_fmcadc5_sync: add a calibration signal generation 2017-04-28 11:13:24 -04:00
Rejeesh Kutty 956753ca9c hdlmake- updates 2017-04-27 15:11:01 -04:00
Rejeesh Kutty 0cb2316cb9 fmcadc5-sync- add ldo psync 2017-04-27 13:26:17 -04:00
Istvan Csomortani 49ef9a589b axi_ad5766: Fix parameter name for up_dac_common 2017-04-27 13:55:16 +03:00
Istvan Csomortani 4e15a21b79 spi_engine_interconnect: Delete dependency defined for S1_CTRL interface
The S1_CTRL interface is not dependent of the number of SDI lines.
2017-04-27 11:28:25 +03:00
Istvan Csomortani 4ceed4d373 util_pulse_gen: Add Makefile 2017-04-27 11:28:25 +03:00
Istvan Csomortani 18a671cdb7 spi_engine: Expose DATA_WIDTH to software
The value of DATA_WIDTH can be read back from register 0x44
The DATA_WIDTH will define the size of a word in a transaction.
2017-04-27 11:28:24 +03:00
Istvan Csomortani 801fb2281e util_pulse_gen: The valid period is stored in pulse_period_d 2017-04-27 11:28:24 +03:00
Istvan Csomortani fbccb377cc adaq7980: Add an trigger generator for SPI offload 2017-04-27 11:28:23 +03:00
Istvan Csomortani a4c422ac4c spi_engine_execution: Define port dependencies for SDI ports 2017-04-27 11:28:21 +03:00
Istvan Csomortani 045cb96744 axi_spi_engine: Define ports dependencies for up_* interface
The up_* interface ports are active just if the MM_IF_TYPE is UP_FIFO.
2017-04-27 11:27:35 +03:00
Istvan Csomortani 9cd218eb90 up_dac_common: Increase datawidth of dac_datarate
In case of high precision devices with just a simple SPI interface
for control and data, the effective data rate can be significatly
lower than the SPI clock, and more importantly there isn't any relation
between the two clock domain.
The rate is defined by a SOT (start of transfer) generator, which
initiates a SPI transfer. Taking the fact that the generator runs
on system clock (100 MHz), and the device can require smaller rate (in kHz domain),
the 7 bit dac_datarate register is just too small.

Therefor increasing to 16 bit.
2017-04-27 11:24:08 +03:00
Istvan Csomortani a2c20551a2 axi_ad5766: Add Makefiles for the core 2017-04-27 11:22:31 +03:00
Istvan Csomortani eba22892b8 axi_ad5766: Preserve consistent coding style 2017-04-27 11:21:15 +03:00
Istvan Csomortani d061104a3c util_pulse_gen: Add configuration interface for 'pulse period'. 2017-04-27 11:21:12 +03:00
Istvan Csomortani 825d46259b interface: Update spi_engine_offload_ctrl definition
Because of the new AD5766 offload module, SDO lines are
defined as 'optional'.
2017-04-27 11:19:22 +03:00
Istvan Csomortani 5c5baf3abf spi_engine: Fix CMD_FIFO_VALID generation
Because of the memory map interface mux, up_waddr_s should be used,
when cmd_fifo_in_valid is generated.
2017-04-27 11:19:20 +03:00
Istvan Csomortani 29f0ce36bb axi_ad5766: Initial commit
This core can be used in conjunction with the SPI_ENGINE, will work
as an offload module, forwarding a data stream to the SPI excecution,
received from a DMA.
2017-04-27 11:16:23 +03:00
Istvan Csomortani fb6e0d3efb spi_engine: Add dependency for unused interfaces 2017-04-27 11:16:19 +03:00
Rejeesh Kutty 5d6b018b2b ad9162- add iq swap 2017-04-26 20:54:47 -04:00
Istvan Csomortani 85a647eda8 axi_ad9361: Fix ad_cmos_out instantiations
This is a patch for 3627b89
2017-04-26 10:39:54 +03:00
Adrian Costina 7cff12107e hdlmake: Fix util_clkdiv Makefile issue. sort library master Makefile 2017-04-26 09:58:17 +03:00
Rejeesh Kutty cfd4e006b3 hdlmake updates 2017-04-25 15:46:26 -04:00
Rejeesh Kutty 804df251a6 axi_fmcadc5_sync- updates 2017-04-25 11:35:37 -04:00
Rejeesh Kutty 81570ada75 axi_fmcadc5_sync- updates 2017-04-25 11:35:37 -04:00
Rejeesh Kutty c248d5ac6a fmcadc5-sync- try sync in hdl 2017-04-25 11:35:37 -04:00
Istvan Csomortani 468965a792 altera/ad_cmos_in: Define supported DEVICE_TYPE options 2017-04-25 12:07:33 +03:00
Istvan Csomortani 52305f74c8 altera/ad_cmos_in|out: Delete redundant parameter 2017-04-25 12:06:33 +03:00
Istvan Csomortani 77eafbcccd avl_dacfifo: Update constarint file 2017-04-25 12:03:46 +03:00
Istvan Csomortani 1ef3fd4668 avl_dacfifo: Fix read/write address switching 2017-04-25 12:03:22 +03:00
Istvan Csomortani 3627b892c3 xilinx/ad_cmos_in|out: Delete redundant parameter
The LVCMOS standard is a single ended IO standard. The SINGLE_ENDED
parameter is redundant in this case.
2017-04-25 11:02:35 +03:00
Istvan Csomortani 4f4ca84813 axi_dacfifo: Fix Makefile 2017-04-24 11:46:29 +03:00
Istvan Csomortani 4007df2094 avl_dacfifo: Update constraints 2017-04-21 17:25:46 +03:00
Istvan Csomortani 89b3f45fff avl_dacfifo: Use the ad_mem_asym for altera 2017-04-21 17:25:46 +03:00
Istvan Csomortani b7bfa2d91f avl_dacfifo: Delete redundant file 2017-04-21 17:25:46 +03:00
Istvan Csomortani 180a80493b avl_dacfifo: Initial commit 2017-04-21 13:26:37 +03:00
Istvan Csomortani 5fe7a1b100 axi_dacfifo: Move the axi_dac_fifo_bypass module to util_dac_fifo_bypass 2017-04-21 13:23:03 +03:00
Istvan Csomortani 50e6fac5dd axi_hdmi_tx: Fix assignment type
The general rule of thumb is to use nonblocking assignments for
sequential always blocks.
2017-04-21 09:35:34 +03:00
Lars-Peter Clausen f319d1b5d4 axi_clkgen: Propagate clock settings to output pins
Calculate the output clock frequencies based on the input clock frequencies
and the default divider settings and configure the output clock pins
accordingly. This allows connected peripherals to infer the frequency of
the clock.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 20:36:33 +02:00
Lars-Peter Clausen af913863d4 axi_clkgen: Infer CLKIN period
Instead of having to manually specify the input clock period infer the
values from the block design. This means that less configuration parameters
need to be changed if the clock input frequency changes.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 20:36:15 +02:00
Lars-Peter Clausen fdedc9568c axi_clkgen: Add interface definitions for clock inputs/outputs
Add interface definition for the input and output clocks. This will allow
the tools to recognize them as clocks and enable things like clock
frequency propagation.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 19:55:57 +02:00
Lars-Peter Clausen 15ce8cc356 axi_clkgen: Add enable parameters for secondary clock inputs/outputs
The secondary clock inputs and outputs of the axi_clkgen are rarely used.
Add enable parameters that need to be explicitly set before they are
available. This allows to hide the secondary clock pins when they are not
used in the block design.

There are currently no projects which use the secondary clock inputs or
outputs so there is no need to set these new parameters anywhere.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 19:55:57 +02:00
Lars-Peter Clausen 886c818b72 axi_clkgen: Add type hints for parameters
Vivado infers the type of floating point type parameters as integer if the
value can be expressed as an integer (i.e. decimal places are 0). To
correctly infer them as floating point parameters add types to the
parameter declaration.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 19:55:56 +02:00
Lars-Peter Clausen 844521c7b1 axi_clkgen: Remove unused parameters for third clock output
The axi_clkgen has no no third clock output, no need to have parameters to
configure it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 19:55:33 +02:00
Istvan Csomortani ba6802409b axi_ad9434: ad_serdes_clk instantiation should reflect all important configurations 2017-04-20 18:52:06 +03:00
Istvan Csomortani 5b164ad4fa ad_serdes_in: Fix generate block 2017-04-20 18:50:00 +03:00
Istvan Csomortani faa5e3d667 ad_serdes_clk: Fix generate block 2017-04-20 18:49:00 +03:00
Istvan Csomortani f0da125a4e ad_mmcm_drp: Fix generate block
Can not be multiple 'if' statements inside a generate block. If there are
multiple cases use if/esle statement, but always should be one single
if/else inside a generate.
2017-04-20 18:43:37 +03:00
Istvan Csomortani 52f0eeff23 axi_ad9434: Port redeclaration as a wire is not allowed 2017-04-20 14:33:13 +03:00
Istvan Csomortani 5294e238d2 axi_ad9250: Port redeclaration as a wire is not allowed 2017-04-20 10:50:21 +03:00
Istvan Csomortani 6ab8624a06 axi_ad9625: Port redeclaration as a wire is not allowed 2017-04-20 10:49:24 +03:00
Lars-Peter Clausen 9f55a703cc axi_dmac: post_propagate(): Handle mappings with multiple address segments
When a mapping has multiple address segments we need to consider all of
them to calculate the required address width.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-19 13:47:02 +02:00
Lars-Peter Clausen 5084e4a8f7 axi_dmac: post_propagate(): Handle address segments with offsets
The address width needs to be large enough to be able to address the
largest possible address. This means the in addition to the address segment
range the specified offset also needs to be considered to calculate the
address width.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-19 13:47:02 +02:00
Istvan Csomortani db0cd63ed3 axi_ad9361: Fix Warning[Synth 8-2611]
In Verilog-2001 standard, redeclaration of an output port as a wire
is not allowed.
2017-04-19 13:52:13 +03:00
Istvan Csomortani 931758b70c ad_tdd_control: Optimize the burst_counter logic
The tdd_burst_counter should be in reset if the tdd_cstate
is not ON. (tdd counter is inactive)
2017-04-19 12:02:31 +03:00
Adrian Costina ac5efc9adc library: axi_i2s_adi, axi_spdif_rx, axi_spdif_tx, util_axis_fifo rename ports to lowercase 2017-04-18 12:17:41 +02:00
Lars-Peter Clausen 8549420af5 axi_dmac: Remove reset from up_rdata and gate when unused
up_rdata is qualified by the up_rack signal. There is no need to reset it
since by the time the signal is read the reset value has already been
overwritten anyway.

Also gate the up_rdata registers if no read operation is in progress. In
this case any changes would be ignored anyway.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:41 +02:00
Lars-Peter Clausen 6ed684714e axi_dmac: Add missing reset for cyclic and xlast flags
Make sure the cyclic and xlast flag registers are covered by the reset signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:41 +02:00
Lars-Peter Clausen f0e8b7adec axi_adc_trigger: Reduce AXI address width
The axi_adc_trigger does not use the full width of the AXI interface
address. It only responds to register access in the first 32 registers.

Reduce the size of the AXI address to 7 bit accordingly. This allows the
scripts to correctly infer the internal register map size which will cause
the interconnect to filter out access to these unused register.

This slightly reduces utilization by getting rid of some pipeline
registers.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:41 +02:00
Lars-Peter Clausen 837b2c02e2 axi_adc_decimate: Reduce AXI address width
The axi_adc_decimate does not use the full width of the AXI interface
address. It only responds to register access in the first 32 registers.

Reduce the size of the AXI address to 7 bit accordingly. This allows the
scripts to correctly infer the internal register map size which will cause
the interconnect to filter out access to these unused register.

This slightly reduces utilization by getting rid of some pipeline
registers.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:41 +02:00
Lars-Peter Clausen 53c8ece8f8 axi_dac_interpolate: Reduce AXI address width
The axi_dac_interpolate does not use the full width of the AXI interface
address. It only responds to register access in the first 32 registers.

Reduce the size of the AXI address to 7 bit accordingly. This allows the
scripts to correctly infer the internal register map size which will cause
the interconnect to filter out access to these unused register.

This slightly reduces utilization by getting rid of some pipeline
registers.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:41 +02:00
Lars-Peter Clausen b24f93a8bd axi_logic_analyzer: Reduce AXI address width
The axi_logic_analyzer does not use the full width of the AXI interface
address. It only responds to register access in the first 32 registers.

Reduce the size of the AXI address to 7 bit accordingly. This allows the
scripts to correctly infer the internal register map size which will cause
the interconnect to filter out access to these unused register.

This slightly reduces utilization by getting rid of some pipeline
registers.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Lars-Peter Clausen d64bd4cec1 axi_dmac: Reduce AXI address width
The AXI DMAC peripheral only uses 11-bit of the register map interface
address. Reducing the signal width to this value allows the scripts to
correctly infer the size of the register map.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Lars-Peter Clausen 9550c7f352 up_axi: Allow to configure AXI address width
Not all peripherals need the full address space. To be able to infer the
size of the address space of a peripheral allow the size of the AXI address
signals to be configurable rather than hardcoding its width to 32 bit.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Lars-Peter Clausen 9f382d56c6 scripts/adi_ip.pl: Infer register map range from address width
Currently the register map range of a peripheral is hardcoded to 64k. Not
all peripherals need that much space though and reducing the size of the
address can reduce the amount of logic required, both in the interconnect
as well as in the peripheral.

Let adi_ip_properties() infer the size of the register map from the number
of bits of the address when creating the register map.

For backwards compatibility limit the register map size to 64k since
currently peripherals have a address width of 32 bits, event if they use
less.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Lars-Peter Clausen 77399ec7aa axi_logic_analyzer: Add missing reset wire declaration
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Adrian Costina 021226bace util_var_fifo: Assign data_out and data_out_valid based on fifo_active
- fixed fifo_active assignments
2017-04-18 12:17:40 +02:00
Adrian Costina f761bf9bab util_var_fifo: Disable BRAMs if the depth of the FIFO is 0. 2017-04-18 12:17:40 +02:00
Adrian Costina 20a223be99 util_var_fifo: Move BRAM outside of the core so that it can be generated using Xilinx IP 2017-04-18 12:17:40 +02:00
Adrian Costina d43ba5d26e axi_ad9963: Integrated ADC/DAC clock enables 2017-04-18 12:17:40 +02:00
Adrian Costina 118dd18ba0 up_dac_common: Added clock enable control for the DAC cores 2017-04-18 12:17:40 +02:00
Adrian Costina 2296ef5882 up_adc_common: Added clock enable control for the ADC cores 2017-04-18 12:17:40 +02:00
Lars-Peter Clausen 4e0d68fde8 axi_dmac: Configure AXI address width according to the mapped address space
Currently the AXI address width of the DMA is always 32-bit. But not all
address spaces are so large that they require 32-bit to address all memory.

Extract the size of the address space that the DMA is connected too and
configure reduce the address size to the minimum required to address the
full address space.

This slightly reduces utilization.

If no mapped address space can be found the default of 32 bits is used for
the address.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Lars-Peter Clausen 3ab1e392c5 axi_ad9963: Disable delay_clk port when IODELAYs are unused
The delay_clk is only used internally when the IODELAYs are enabled. This
means the port has no function when the IODELAYs are disabled so hide the
port in that case.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Lars-Peter Clausen f869ac9ed2 scripts/adi_ip.tcl: adi_set_ports_dependency(): Allow to specify tie-off value
Typically when a port has a enablement dependency it also should have a
tie-off value to the port is connected to when disabled.

Make it possible to specify this tie-off value when calling
adi_set_ports_dependency().

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Lars-Peter Clausen 508a783f39 axi_dac_interpolate: Register output mux signal
The output data mux is used to bypass the filter when it is not used. Which
setting is used for the mux depends on the 3-bit filter_mask signal.
Registering the control logic into a single bit signal reduces the amount
of routing resources required. Since changing the filter_mask settings is
asynchronous to the processing anyway the extra clock cycle delay
introduced by this change does not affect behaviour.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Lars-Peter Clausen 834fcb7e27 axi_dac_interpolate: Reduce filter_mask signal width
Only the lower 3 bits of the filter_mask signal are used, no need to keep
the other bits around.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Lars-Peter Clausen 9c2c50728c axi_dac_interpolate: Move processing pipeline to own sub-module
Move the processing pipeline of the axi_adc_decimate core to its own
sub-module. This makes it easier to simulate the processing independent of
the register map.

Also since the filter is two instances of the same logic, one for each
channel, let the new sub-module model one channel and instantiate it twice.
This allows to change the implementation without having to change the same
code twice.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Lars-Peter Clausen a02a763139 axi_adc_decimate: Do proper sign extension in bypass mode
The output data of the decimation block is 16-bit signed. Properly sign
extend the 12-bit input signal when the filter is bypassed.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Lars-Peter Clausen 19ca0b3073 axi_adc_decimate: Gate unused filter parts
The minimum number of bits required for the adders in a CIC filter depends
on the decimation rate. Higher decimation factors require more bits. This
means for a multirate filter the size of the logic structures is determined
by the highest supported rate.

The current implementation of the filter always uses all bits of the
structure to compute the results, that means even when running with the
lowest decimation factor all the bits that are required for the highest
decimation factor are used. This will work fine as additional bits do not
affect the output of the filter.

This patch implements dynamic partial gating of the filter structure based
on the selected decimation factor. Bits that are not required for a certain
rates are gated and the carry bits are masked from propagating through the
adder chain. This results in significant power savings at smaller
decimation factors.

This means that the filter itself is now using more power the higher the
decimation rate. But this is offset by the reduced data output rate running
subsequent processing stages at a lower rate and reducing power consumption
there. This results in a more or less flat power profile regardless of
decimation factor.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Lars-Peter Clausen 17dff9ce90 util_cic: Allow partial gating of CIC comb and int stages
Allow to split a CIC int or comb block into multiple stages and be able to
dynamically gate some of the stages. Also prevent carry propagation in
gated stages to keep the adder output constant.

This is useful for multi-rate filter where not all bits are needed all the
time.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Lars-Peter Clausen 3e7325b29a axi_adc_decimate: Re-implemented FIR filter
The minimum decimation rate of the CIC block is five, this means data
arrives at the FIR filter at most every five clock cycles. The decimation
rate of the filter is two so the filter produces an output at most every
ten clock cycles. This allows for ten clock cycles to compute the result.

The current implementation of the filter uses a fully pipelined
architecture with one multiplier for each coefficient. Which then do work
for one clock cycle and sit idle for the next nine clock cycles.

Rework the filter to be sequential reducing the number of required
multipliers to one. In addition exploit the symmetric structure of the
filter to make use of the preadder reducing the required multiply
operations by two.

This significantly reduces the logic utilization of the filter as well as
moderately reduces power consumption.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Lars-Peter Clausen 737418a1b0 axi_adc_decimate: Use sequential processing for CIC comb stage
The minimum decimation of the CIC block is 5. This means new data arrives
at the comb stages at most every 5 clock cycles. Rather than letting the
logic sit idle during those 4 extra cycles use it to sequentially process
the comb stages of the filter. This reduces the logic utilization of the
filter by quite a bit.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Lars-Peter Clausen a64e94a109 axi_adc_decimate: Register output mux control signal
The output data mux is used to bypass the filter when it is not used. Which
setting is used for the mux depends on the 3-bit filter_mask signal.
Registering the control logic into a single bit signal reduces the amount
of routing resources required. Since changing the filter_mask settings is
asynchronous to the processing anyway the extra clock cycle delay
introduced by this change does not affect behaviour.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Lars-Peter Clausen 00c215ae69 axi_adc_decimate: Re-implement CIC filter
Re-implement the CIC using the basic building blocks from the util_cic
library.

This new implementation is structurally equivalent to the previous version,
but will be used as a platform for implementing changes that will improve
area and power consumtion of the filter

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Lars-Peter Clausen 450c5ac74a Add CIC filter helper module
Add a helper module that provides the building blocks of a CIC filter.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Lars-Peter Clausen f1edcb02ac axi_adc_decimate: Reduce filter_mask register size
Only the 3 lower bits of the filter_mask register are used. No need to keep the other bits around.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
Lars-Peter Clausen 927508404e axi_adc_decimate: Move processing pipeline to own sub-module
Move the processing pipeline of the axi_adc_decimate core to its own
sub-module. This makes it easier to simulate the processing independent of
the register map.
2017-04-18 12:17:40 +02:00
Adrian Costina 8ba86cb75c axi_logic_analyzer: Allow changing data pins direction to output only after data is available from the DMA or if the output is set from a register for that specific pin 2017-04-18 12:17:40 +02:00
Adrian Costina 8476d9d59a axi_logic_analyzer: Allow only data[0] to be used as alternative clock.
- drive all logic on clk_out instead of clk
2017-04-18 12:17:39 +02:00
Adrian Costina 3c13aa49eb axi_ad9963: Changed TX path from serdes to ddr.
- remove delay control related logic
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 77b453ac0d axi_dmac: Make debug register optional
The debug registers are useful during development but are rarely used in a
production design. Add a option that allows to disable them, this reduces
the resource utilization of the DMAC.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 547dc04857 axi_ad9963: Sign extend ADC data when processing is bypassed
Match the behaviour of the processing data path and sign extend the output
data to 16-bit.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen a0e30a2211 util_axis_fifo: Improve clock gating of registers and BRAM
Currently the BRAM and data registers in the util_axis_data are ungated
when the FIFO is ready to receive data. This good for high-performance
since it reduces the number of control signals. But it is bad from a power
point of view since it causes additional reads and writes.

Change the core gate the BRAM and data register if either the consumer is
not ready to accept data or the producer has no data to offer.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 72cdd846b0 axi_ad9963: Allow to disable the IDELAYs on the ADC data path
Not all designs need the IDELAYs. Disabling them can reduce power consumption of the system.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 09ffe42603 ad_lvds_in: Allow to disable IDELAY
The IDELAY is not always required, but it eats up power when instantiated. Allow to disable it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 45f87b46c2 ad_lvds_in: Use "SAME_EDGE" mode
Currently the IDDRs are configured in SAME_EDGE_PIPELINED mode, but then
the negative data is delayed by an additional clock cycle. This is the same
behaviour as using the IDDR in SAME_EDGE mode.

Switching to SAME_EDGE mode removes extra pipelining registers while
maintaining the same behaviour.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 0e2b47e517 axi_adc_trigger: Temporarily disable trigger reporting in register map
The current implementation doesn't quite work right when the interface
clock is slower than the trigger clock and also causes timing issues.
Disable it temporarily until a proper CDC transfer is implemented.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Adrian Costina be6fa287fa axi_dac_interpolate: Make dac_reset external 2017-04-18 12:17:39 +02:00
Adrian Costina 7227e74444 axi_adc_decimate: Make adc_reset external 2017-04-18 12:17:39 +02:00
Adrian Costina 094872619d axi_ad9963: Separated adc/dac clock and reset 2017-04-18 12:17:39 +02:00
Adrian Costina 9f8fd5c922 axi_ad9963: updated tx path
- removed pll for power saving, added serdes circuitry instead
2017-04-18 12:17:39 +02:00
Adrian Costina fc7f2ef11b ad_serdes_out: allow selection between DDR/SDR configuration and output single ended data 2017-04-18 12:17:39 +02:00
Adrian Costina 166a4c53d5 ad_serdes_clk: allow for single ended clock input, made BUFR_DIVIDE configurable 2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 71469490c6 Add a helper module to combine a AXI read-only and a AXI write-only interface into a read-write interface
The read and write interfaces of a AXI bus are independent other than that
they use the same clock. Yet when connecting a single read-only and a
single write-only interface to a Xilinx AXI interconnect it instantiates
arbitration logic between the two interfaces. This is dead logic and
unnecessarily utilizes the FPGAs resources.

Introduce a new helper module that takes a read-only and a write-only AXI
interface and combines them into a single read-write interface. The only
restriction here is that all three interfaces need to use the same clock.

This module is useful for systems which feature a read DMA and a write DMA.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 3e0b337eae axi_ad9963: Remove extra pipeline stages on register read path
The register read logic is not that complicated that it needs two extra
pipeline stages. It can easily be condensed into a single combinatorial and
still meet timing with large margins.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 64dfa0432d axi_ad9963: Disable unused features of the register map
Disable registers in the register map which are not needed for this core.
This reduces the utilization of the core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 957730c421 up_dac_common: Allow to disable GPIO registers
Not all peripherals use the GPIO register settings, but the registers still
take up a fair amount of space in the register map. Add options to allow to
disable them when not needed. This helps to reduce the utilization for
peripherals where these features are not needed.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 0ae0da488b up_adc_common: Allow to disable GPIO and START_CODE registers
Not all peripherals use the GPIO and START_CODE register settings, but the
registers still take up a fair amount of space in the register map. Add
options to allow to disable them when not needed. This helps to reduce the
utilization for peripherals where these features are not needed.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:38 +02:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
Istvan Csomortani 3f0633aadc spi_engine: Fix CMD_FIFO_VALID generation
Because of the memory map interface mux, up_waddr_s and up_wreq_s should be
used, when cmd_fifo_in_valid is generated.
2017-04-12 14:57:22 +02:00
Istvan Csomortani c1bdfca4c3 library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
Istvan Csomortani c637d848bb util_clkdiv: constraints should be applied LATE for this core 2017-04-03 18:14:29 +03:00
Istvan Csomortani e0efbe210e constraints: constraint files should be specified at adi_ip_files 2017-04-03 18:12:28 +03:00
Rejeesh Kutty 2f023437b4 adi_ip- remove adi_ip_constraints 2017-04-02 10:42:51 -04:00
Rejeesh Kutty d916697263 adi_ip- a little rearrangement 2017-04-01 09:04:35 -04:00
Istvan Csomortani fd56b5a6d3 axi_ad9122: Update constraint files 2017-03-31 10:13:42 +03:00
Istvan Csomortani c46989e4e8 Makefile: Update Makefiles for libraries 2017-03-30 18:33:22 +03:00
Lars-Peter Clausen 495d2f3056 axi_dmac: Propagate awlen/arlen width through the core
Depending on whether the core is configured for AXI4 or AXI3 mode the width
of the awlen/arlen signal is either 8 or 4 bit. At the moment this is only
considered in top-level module and all other modules use 8 bit internally.
This causes warnings about truncated signals in AXI3 mode, to resolve this
forward the width of the signal through the core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-30 17:19:38 +02:00
Istvan Csomortani ebfed4b24b ad_axi_ip_constr.xdc: Delete file 2017-03-30 16:16:02 +03:00
Istvan Csomortani 873fbfd6d7 library: Update scripts with new constraints
Update all IPs tcl scripts with the new constraints files.
Refer to commit 335fef0.
2017-03-30 16:16:02 +03:00
Istvan Csomortani 31a5c674f2 fmcomms2: Update constraints file paths 2017-03-30 16:16:02 +03:00
Istvan Csomortani 8ba6012b6b restructure: Move xilinx specific constraints to /library/xilinx/common/ 2017-03-30 16:16:02 +03:00
Lars-Peter Clausen 983e56d72c ad9963: Remove localparams from module parameter list
Declaring local parameters in the module parameter list is not valid
verilog. For some reasons Vivado accepts it nevertheless so the code has
worked so far. But this is not true for other tools, so move the local
parameter definitions inside the module body.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-30 11:40:28 +02:00
Istvan Csomortani 1d448f0013 adi_ip: Set up SCOPE_TO_REF for xdc and save the core 2017-03-29 18:40:24 +03:00
Istvan Csomortani ea7e93d27f fmcomms2: Use the new constriants from 335fef0 2017-03-29 18:36:09 +03:00
Istvan Csomortani 335fef0f42 ad_axi_ip_constr: Split up this constraint file into separate files
For experimentation, to solve a constraint scoping issue, split up the
ad_axi_ip_constraint file into separate constraints file, in function
of there parent module.
2017-03-29 18:31:40 +03:00
Rejeesh Kutty 2419b3626b ad9684- fix sdc typo 2017-03-23 12:49:44 -04:00
Rejeesh Kutty ae0f4672b2 daq1/a10gx- fix project to compile 2017-03-23 09:46:40 -04:00
Rejeesh Kutty 8063ba2b66 make updates 2017-03-20 16:05:18 -04:00
Rejeesh Kutty c277b39796 arradio/c5soc- critical warnings fix 2017-03-20 12:14:13 -04:00