Istvan Csomortani
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fbafaa8507
|
MicroBlaze base system: Fix a few net names
Every interconnect interface net name follows the convention:
<interconnect name>_<interface name>
No changes in logic or any connection!
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2014-04-01 10:40:35 +03:00 |
Adrian Costina
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a881557645
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base_design: Fixed AC701 and VC707 contstraints
AC701: Modified the IOSTANDARD for some of the pins to correspond to the
AC701 user guide.
VC707: Fixed naming for some system clocks
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2014-03-31 17:38:20 +03:00 |
|
Istvan Csomortani
|
0f10623be4
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AC701/VC707: Define common variables
Define variables sys_zynq, sys_mem_size, sys_addr_cntrl_space.
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2014-03-25 14:24:51 +02:00 |
|
Istvan Csomortani
|
b94acf78aa
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AC701 bases sys: Add an auxiliary cpu interconnect
- Add an auxiliary cpu interconnect, the KC705 base system was
used as reference
- Base system is tested and working
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2014-03-24 13:01:52 +02:00 |
|
Istvan Csomortani
|
8a08031dce
|
AC701: Modify interrupt concatenation
- Interrupt concatenation is the same as in case of KC705
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2014-03-24 10:20:56 +02:00 |
|
Istvan Csomortani
|
3a0d1282b7
|
Fix the remaining issues
- Swap the IO locations of ports vsync and hsync
- Change the mem_interconnect optimization strategy to Maximize
Performance
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2014-03-20 14:36:01 +02:00 |
|
Istvan Csomortani
|
7cdab9b5b0
|
Change the internal clock generator to Clock Wizard
- Using a Clock Wizard Module, in place of the DDR Controler's MMCM for internal clock
generation.
|
2014-03-18 17:24:45 +02:00 |
Rejeesh Kutty
|
5c3b65d01b
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adv7511: kc705/ac701 updates
|
2014-03-06 09:36:50 -05:00 |
|
Rejeesh Kutty
|
360f10395a
|
initial checkin
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2014-03-03 13:42:25 -05:00 |