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1915 Commits (297940d5d9cec65e7f9d1edb6a1bc7d48deca5f7)

Author SHA1 Message Date
Laszlo Nagy bfc8ec28c3 util_axis_fifo: instantiate block ram in async mode 
In cases when a shallow FIFO is requested the synthesizer infers distributed RAM
instead of block RAMs. This can be an issue when the clocks of the FIFO are
asynchronous since a timing path is created though the LUTs which implement the
memory, resulting in timing failures. Ignoring timing through the path is not a
solution since would lead to metastability.
This does not happens with block RAMs.

The solution is to use the ad_mem (block RAM) in case of async clocks and letting
the synthesizer do it's job in case of sync clocks for optimal resource utilization.
 2018-04-11 15:09:54 +03:00
Istvan Csomortani 3277ea4be0 ad_dcfilter: Enable output registers in DSP48E1 
Pipelining the DSP48 output will improve performance and often saves power so
it is suggested whenever possible to fully pipeline this function.
 2018-04-11 15:09:54 +03:00
Istvan Csomortani 09a6eb5360 up_dac_common: Explicitly define boolean parameter as a 1 bit value 2018-04-11 15:09:54 +03:00
Istvan Csomortani a1e2b60cb3 ad_xcvr_rx_if: rx_ip_sof_d register has a width of 4 bits 2018-04-11 15:09:54 +03:00
Istvan Csomortani b6770effc5 avl_dacfifo: Add missing wire declaration 2018-04-11 15:09:54 +03:00
Istvan Csomortani f100a6bf21 avl_dacfifo: Delete deprecated false path definition 2018-04-11 15:09:54 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
Istvan Csomortani 34994222b4 license: Update old license headers 2018-04-11 15:09:54 +03:00
Laszlo Nagy ee79ba5686 axi_hdmi_tx: removed unused registers 2018-04-11 15:09:54 +03:00
Istvan Csomortani 9a76bd4536 axi_adxcvr: Set the init value of the configuration registers 2018-04-11 15:09:54 +03:00
Istvan Csomortani 571b721274 util_adxcvr: CPLLPD should be used for reset 
For CPLL reset the CPLLPD ports should be used, instead of the
CPLLRESET. The recommended reset width is above 2us.
See UG576 pg. 60 for more detail.
 2018-04-11 15:09:54 +03:00
Istvan Csomortani 4e60f15e7f axi_clkgen: Add a parameter to control the clock source options 
Add a parameter to the control the clock source option of the MMCM. If
the MMCM has only one clock source the CLKSEL pin will be tied to VDD.

The previous version added a redundant path between the CLKSEL port and
register map.
 2018-04-11 15:09:54 +03:00
Rejeesh Kutty 72431ff952 a10soc: Connect AXI register reset 2018-04-11 15:09:54 +03:00
Adrian Costina a5407702bb util_adxcvr: Don't show reset ports for disabled lanes 2018-04-11 15:09:54 +03:00
Laszlo Nagy 0d01c08b00 util_[c|u]pack_dsf: clear syntehsis warnings 
Remove unused registers and move register definitions to the generate block
that is actually using it.
 2018-04-11 15:09:54 +03:00
Laszlo Nagy bce0cf8e22 util_[w|r]fifo: Reduce synthesis warnings 2018-04-11 15:09:54 +03:00
Laszlo Nagy eedd8ed5d8 up_delay_cntrl: Fix synthesis warnings, no functional changes 
Reduce the number of synthesis warnings with the help of a generate
statement. When the block is disabled do not generate any logic.
 2018-04-11 15:09:54 +03:00
Laszlo Nagy b4ab639db5 up_[adc|dac]_common: Define the DPR registers only when the interface is enabled 2018-04-11 15:09:54 +03:00
Laszlo Nagy 5cba46165a axi_dmac: fix synthesis warnings 
Separated the 2D transfer registers to a separate generate block
 2018-04-11 15:09:54 +03:00
Laszlo Nagy 4bcf45a17a common: clean up synthesis warnings 
Removed unused registers and define registers only when they are in use.
 2018-04-11 15:09:54 +03:00
Laszlo Nagy b6d2def504 axi_ad9361: clear synthesis warnings 
Defined the delay registers only when they are used.
 2018-04-11 15:09:54 +03:00
Adrian Costina 5bfc585524 axi_dmac: Added MAX_BYTES_PER_BURST and DISABLE_DEBUG_REGISTERS parameters to Intel IP 2018-04-11 15:09:54 +03:00
Adrian Costina 25ffb91dc6 axi_hdmi_tx: Updated .sdc constraints 2018-04-11 15:09:54 +03:00
Adrian Costina a0cb3af11d axi_hdmi_tx: Use abstract multiplier module supporting both Xilinx and Intel FPGAs 2018-04-11 15:09:54 +03:00
Istvan Csomortani d13ff8df1e axi_dmac: In SDP mode REGCEB is connected to GND 
In newer version of Vivado (e.g. 2017.4) the REGCEB pin of the block ram
macro is connected to ground. So the following false path became
redundant.
 2018-04-11 15:09:54 +03:00
Istvan Csomortani fcbc977cd8 axi_ad7616: Add missing port to instantiation 2018-04-11 15:09:54 +03:00
Istvan Csomortani f605b428fc spi_engine:axi_spi_engine: Add missing port to instantiations 2018-04-11 15:09:54 +03:00
Istvan Csomortani 7d0b162eda axi_ad9963: Fix port dependency definition 2018-04-11 15:09:54 +03:00
Istvan Csomortani a7b98c397a ad_tdd_control: Fix the tdd_burst_counter implementation 2018-04-11 15:09:54 +03:00
Istvan Csomortani cd94f2f249 util_axis_upscale: Initial commit 
This module upscale an n*sample_width data bus into a 16 or 32*n data
bus. The samples are right aligned and supports offset binary or two's
complement data format.
 2018-04-11 15:09:54 +03:00
Istvan Csomortani 269ae40f66 spi_engine: Add support for 8 SDI lines 2018-04-11 15:09:54 +03:00
Istvan Csomortani e16f45c792 util_pulse_gen: Use equal-to for counter reset 2018-04-11 15:09:54 +03:00
Adrian Costina 017dcaed82 up_[adc|dac]_common: DRP_DISABLE should be boolean 2018-04-11 15:09:54 +03:00
Adrian Costina d3bfb33871 constraints: up_xfer_cntrl and up_xfer_status have its own constraints 
The up_xfer_cntrl and up_xfer_status modules have its own constraints files
in library/xilinx/common. Each IP which has an instance of these
modules, have to use these constraints files.

The following IPs were modified:
  - axi_adc_decimate
  - axi_adc_trigger
  - axi_dac_interpolate
  - axi_logic_analyzer
 2018-04-11 15:09:54 +03:00
Laszlo Nagy ae02773480 axi_dacfifo: Rewrote constraints to be more specific 
Some of the wildcards matched too many paths and disabled the timing
checks on intraclock paths.
 2018-04-11 15:09:54 +03:00
Adrian Costina b2d63bf9e0 axi_ad9434: Make adc_enable controllable from the channel register map 2018-04-11 15:09:54 +03:00
Adrian Costina 493fc1d48b axi_*: Fix instantiation of up_[adc|dac]_[common|channel] 
A couple of new parameters and new ports are missing in several
up_[adc|dac]_[common|channel] instance, and generates warnings. The rule of
thumb is to use full instantiations, defining all the existing parameter and
ports of the module.

Fix all the instantiation of up_[adc|dac]_[common|channel], by defining all its
parameters and ports.
 2018-04-11 15:09:54 +03:00
Adrian Costina 74b922f9f8 axi_*: Infer clock and reset signals of an IP 
A clock sink must be connected to clock source, and a reset sink to
reset source, otherwise the tool will throw a synthesis warning.
By properly inferring all the reset and clock signals of an IP, we can
get rid of unwanted warning messages.

The following IPs tcl script was updated:
  - axi_ad9434
  - axi_hdmi_tx
  - util_cpack
  - util_adxcvr
  - axi_ad6676
  - axi_ad9625
  - axi_ad9379
  - axi_ad9265
  - util_tdd_sync
  - util_rfifo
  - util_wfifo
  - axi_ad9361
  - axi_ad9467
  - util_upack
  - axi_dacfifo
  - axi_ad9152
  - axi_ad9680
  - util_clkdiv
  - axi_ad9122
  - axi_ad9684
  - axi_mc_speed
  - axi_mc_current_monitor
  - axi_mc_controller
  - util_gmii_to_rgmii
  - util_adxcvr
  - axi_ad9379
  - axi_hdmi
  - library
  - axi_fmcadc5_sync
  - util_adcfifo
  - util_mfifo
  - axi_jesd204_rx
  - axi_jesd204_tx
  - axi_ad9361
  - axi_adxcvr_ip
 2018-04-11 15:09:54 +03:00
Istvan Csomortani 3b34e8b594 up_clock_com: Fix the false path definitions for CDCs 2018-04-11 15:09:54 +03:00
AndreiGrozav c313c67585 axi_adcfifo_constr.xdc: Add missing backslash to command 2018-04-11 15:09:54 +03:00
Istvan Csomortani d81f605ae9 axi_ad9162: Fix code alignment, no functional changes 2018-04-11 15:09:54 +03:00
Istvan Csomortani 758c617c77 common/up_* : Make up_rstn synchronous to up_clk 
The up_rstn is driven by s_axi_resetn, which is generated by a
Processor System Reset module. (connected to port peripheral_aresetn)
Therefor using this reset signal as an asynchronous reset is redundant,
and a bad design practice at the same time. Asynchronous reset should be
used if it's inevitable.
 2018-04-11 15:09:54 +03:00
Adrian Costina 8234ba1029 scripts:adi_ip: Update web address format 
Change format for web address so that IP GUI considers it valid
 2018-04-11 15:09:54 +03:00
Istvan Csomortani 7c04e36656 scripts: Message severity changes on Vivado 
Vivado sometimes generates semi-valid or invalid warnings and critical warnings.
In the past these messages were silenced, by changing its message severity.
These setups were scattered in multiple scripts. This commit is an attempt
to centralize it and make it more maintainable and easier to review it.
 2018-04-11 15:09:54 +03:00
Istvan Csomortani 47e95fc4a9 scripts: Update tools for the next release 
The next supported tool versions are:
  + Vivado 2017.4.1
  + Quartus 17.1
 2018-04-11 15:09:54 +03:00
Istvan Csomortani 377848ef52 cftl: Delete unused projects and libraries 2018-04-11 15:09:54 +03:00
Istvan Csomortani bee392253b jesd204:tb: Fix the loopback_tb test bench 
The jesd204_rx instantiation contained a port that did not exist. (phy_ready)
 2018-03-28 15:19:18 +01:00
Adrian Costina 9baf910339 axi_logic_analyzer: Fix push-pull/open-drain selection 2018-03-07 10:19:51 +02:00
Istvan Csomortani a740b6012f Make: Use $(MAKE) for recursive make commands 
This commit should resolve the issue #64.

Recursive make commands should always use the variable MAKE, not the explicit
command name ‘make’.
 2018-03-07 07:40:19 +00:00
Lars-Peter Clausen e95f1b282e Remove unused Q_OR_I_N parameter from JESD204 ADC cores 
The cores that handle the JESD204 ADC cores do not feature IQ correction
logic. The Q_OR_I_N parameter for the channel modules is unused, so remove
it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2018-02-20 16:33:16 +01:00