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3 Commits (27c3231c1b6ac82e6355a795feb298dd738ad8c1)

Author SHA1 Message Date
Lars-Peter Clausen d72fac4b1e Add missing timescale annotations 
For consistent simulation behavior it is recommended to annotate all source
files with a timescale. Add it to those where it is currently missing.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2018-10-17 10:32:47 +03:00
Laszlo Nagy 3f94fec620 axi_dmac/dma_write_tb: added data integrity check 
Added passing condition checking.
Added variable request sizes
 2018-05-03 14:49:06 +02:00
Lars-Peter Clausen 24d17e8bcc axi_dmac: Add transfer testbenches 
Add simple transfer testbenches that test the read and write to AXI memory
paths of the DMAC.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2018-05-03 14:49:06 +02:00