Commit Graph

56 Commits (27bb69b44c02ccf907bdc83749845cf11fe87940)

Author SHA1 Message Date
Istvan Csomortani fbafaa8507 MicroBlaze base system: Fix a few net names
Every interconnect interface net name follows the convention:
	<interconnect name>_<interface name>
	No changes in logic or any connection!
2014-04-01 10:40:35 +03:00
Adrian Costina a881557645 base_design: Fixed AC701 and VC707 contstraints
AC701: Modified the IOSTANDARD for some of the pins to correspond to the
AC701 user guide.
VC707: Fixed naming for some system clocks
2014-03-31 17:38:20 +03:00
Istvan Csomortani 0f10623be4 AC701/VC707: Define common variables
Define variables sys_zynq, sys_mem_size, sys_addr_cntrl_space.
2014-03-25 14:24:51 +02:00
Istvan Csomortani aa7b0bb4dd VC707 basesys: General fixes, actual status: working
- Add an auxiliary cpu interconnect
	- Add an auxiliary interrupt concatenation module
	- Add new MIG file, current frequency of the DDR interface is 100
	  Mhz
	- Memory interconnect optimisation strategy is 'Maximize
	  Performance'
2014-03-24 13:07:48 +02:00
Istvan Csomortani 75963ab376 Initial check in of VC707 base project
- All source files for the VC707 base project
	- Update the common base system to the new naming convention
2014-03-10 17:26:17 +02:00
Rejeesh Kutty ddac1a8834 added common board files 2014-02-28 21:17:01 -05:00