zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
3,862 Commits
1 Branch
0 Tags
23 MiB
Commit Graph

22 Commits (26822af7e1a52ac27b2169123c7f875f7ba10c45)

Author SHA1 Message Date
Istvan Csomortani 9055774795 all: Update license for all hdl source files 
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
 2017-05-17 11:52:08 +03:00
AndreiGrozav 0e1e507541 axi dac cores: Add missing ports to up_dac_common instance 2017-05-12 13:37:34 +03:00
Rejeesh Kutty 1ef064ac03 axi_ad9361- add receive init delay 2017-03-13 16:28:38 -04:00
Rejeesh Kutty 1a11e28821 ad9361- dac data path split 2016-09-23 16:13:46 -04:00
Istvan Csomortani 913eafed48 up_drp : Update the DRP interface to support Altera platforms 2016-09-21 15:00:45 +03:00
Istvan Csomortani a183e51a12 axi_ad9361: Add parameter R1_MODE_EN 
R1_MODE_EN can disable the second I/Q channel of the core. This way
the user can save resources by cutting down the size of the core.
 2016-09-09 16:34:11 +03:00
Rejeesh Kutty 9799599eee library/ad9361- add dac clk sel 2016-08-26 10:31:00 -04:00
Rejeesh Kutty 583ef82fd0 ad9361- cmos mode 2016-03-04 10:39:48 -05:00
Rejeesh Kutty 74e72021f7 ad9361- ensm through dev-if 2015-08-27 11:41:53 -04:00
Istvan Csomortani 57cfb7cfb1 hdl/library: Update the IP parameters 
The following IP parameters were renamed:

PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
 2015-08-19 14:11:47 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file 
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-06-26 11:07:10 +02:00
Rejeesh Kutty 297e885981 library- drp moved to up-clock domain 2015-06-01 14:52:52 -04:00
Rejeesh Kutty 2bad47cf4f delay-cntrl: up-clk, direct access + tx 2015-05-18 14:28:20 -04:00
Rejeesh Kutty de33722470 up/constr: independent read/write and local constraints 2014-10-02 14:35:59 -04:00
Lars-Peter Clausen 50faf0c53a Remove executable flags from non-exectuable files 2014-09-09 15:05:06 +02:00
Rejeesh Kutty b6052773b7 added adc/dac gpio registers 2014-06-27 14:45:58 -04:00
Rejeesh Kutty e650253013 library: register map changes and for mathworks 2014-06-24 14:22:05 -04:00
Adrian Costina bef6a9c32c axi_ad9361: Split dma data into individual channels for both ADC and DAC 2014-06-07 17:15:31 +03:00
Rejeesh Kutty 3aed3ba71c axi_ad9361: fmcomms5 changes 2014-05-19 12:41:12 -04:00
ATofan 5aac9d7288 FMCOMMS2 added sync option 
Added signals to allow synchronisation of multiple AD9361.
 2014-04-10 10:46:42 +03:00
Rejeesh Kutty ad491e92ab changed pcore version and made it local (top shouldn't override) 2014-03-14 12:02:16 -04:00
Rejeesh Kutty 580808e146 axi_ad9361: added 2014-03-11 20:01:55 -04:00