Commit Graph

57 Commits (26822af7e1a52ac27b2169123c7f875f7ba10c45)

Author SHA1 Message Date
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Rejeesh Kutty 1ef064ac03 axi_ad9361- add receive init delay 2017-03-13 16:28:38 -04:00
AndreiGrozav 9d6c93a5d8 Fix warnings 2016-11-14 15:17:15 +02:00
Rejeesh Kutty a9d03af771 altera- serdes changes 2016-10-28 14:09:18 -04:00
AndreiGrozav 52194f0fea axi_ad9361: Add DRP connection to the interface module 2016-10-11 17:59:12 +03:00
Istvan Csomortani 43b3761b80 axi_ad9361: Flop the tx and rx valid 2016-10-03 12:24:04 +03:00
Rejeesh Kutty b4fac96aad axi_ad9361- independent disables 2016-09-28 15:45:27 -04:00
Istvan Csomortani f7fb3ccaca axi_ad9361: Change the data path gating
Bring up the datapath gating from the TDD controller module.
2016-09-28 16:36:13 +03:00
Rejeesh Kutty 1a11e28821 ad9361- dac data path split 2016-09-23 16:13:46 -04:00
Rejeesh Kutty 7be6168b2e ad9361- adc data path split 2016-09-23 13:42:14 -04:00
Istvan Csomortani 2159f78c80 axi_ad9361: Delete invalid assignment of a generated wire 2016-09-16 17:38:08 +03:00
Istvan Csomortani a183e51a12 axi_ad9361: Add parameter R1_MODE_EN
R1_MODE_EN can disable the second I/Q channel of the core. This way
the user can save resources by cutting down the size of the core.
2016-09-09 16:34:11 +03:00
Istvan Csomortani e42206e510 axi_ad9361: Add a TDD enable/disable parameter 2016-09-09 14:38:28 +03:00
Istvan Csomortani be41a8bcaa axi_ad9361: Delete debug ports of the tdd module 2016-09-09 14:38:28 +03:00
Rejeesh Kutty 9799599eee library/ad9361- add dac clk sel 2016-08-26 10:31:00 -04:00
Rejeesh Kutty bb4ed42a93 ad9361- add missing wires 2016-05-18 13:24:13 -04:00
Rejeesh Kutty 3b5e44e37d library/axi_ad9361: mmcm rst for plls 2016-05-04 13:42:12 -04:00
Rejeesh Kutty 243d3e6e41 ad9361- a10soc sdc files 2016-04-29 10:17:35 -04:00
Rejeesh Kutty 583ef82fd0 ad9361- cmos mode 2016-03-04 10:39:48 -05:00
Istvan Csomortani a747fad540 axi_ad9361: tx_valid must be controlled by the TDD controller 2016-02-12 14:33:34 +02:00
Istvan Csomortani e381d5170c util_tdd_sync: Update the synchronization interface
Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-12 14:27:37 +02:00
Istvan Csomortani 12c95b059d ad_tdd_control: Remove tdd_enable_synced control line
For a better timing and control, the valid control lines are gated with flops, instead of combinatorial logic.
This is the main reason why we do not need the tdd_enable_synced signal anymore. The out coming data is delayed by one clock cycle to keep data and control lines synced.
2015-12-03 11:16:28 +02:00
Istvan Csomortani fc0f4bc414 axi_ad9361: Delete the old sync generator from the core
+ Define two control signal for util_tdd_sync : tdd_sync_en and tdd_terminal_type
+ Delete to old ad_tdd_sync.v instances from the core
+ Update Make files
+ Update ad_tdd_control: add additional CDC logic for tdd_sync (the sync comes from another clock domain)
+ Update the ad_tdd_sync module: it's just a simple pulse generator, the pulse period is defined using a parameter, pulse width is fixed: 128 x clock cycle
+ Update TDD regmap: tdd sync period is no longer software defined
2015-11-11 11:06:19 +02:00
Istvan Csomortani 85ffc25ec5 ad_tdd_sync: Update the synchronization logic
The synchronization interface is a single bidirectional line. Output for Master, input for Slave.
The sync_period value is relative to frame length and the digital interface clock. The actual synchronization
period will be: sync_period * frame_length * fb_clock_cycle
2015-09-09 12:31:58 +03:00
Rejeesh Kutty 2259b6cbf7 ad9361- ensm through dev-if 2015-08-27 11:41:48 -04:00
Istvan Csomortani 57cfb7cfb1 hdl/library: Update the IP parameters
The following IP parameters were renamed:

PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
Istvan Csomortani 10d9de39a1 axi_ad9361/tdd: Update the synchronization logic
The master will regenerate a sync pulse periodically. The period can be defined by software.
2015-08-19 12:21:23 +03:00
Istvan Csomortani bcee3e04d4 fmcomms2_tdd: Update tdd_enabaled path
This line controls the mux, which switch between hdl and software (GPIO) control of the ENABLE/TXNRX pins.
Fix the broken path and change the name from "tdd_enable" to "tdd_enabled".
2015-08-19 12:14:05 +03:00
Istvan Csomortani d2c99acae8 fmcomms2/TDD: Update synchronization interface
Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 15:14:36 +03:00
Istvan Csomortani 8e631e56d6 fmcomms2: Add a synchronization interface for TDD mode.
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write  0x01 into TDD register 0x50.
2015-07-28 14:42:54 +03:00
Istvan Csomortani 9f7fff2d2f axi_ad9361/tdd: Add new control signals to the TDD data flow control logic
Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 14:10:49 +03:00
Istvan Csomortani a497dcabb5 axi_ad9361: Bring up the tdd_enable bit
This line will be the selection bit of the GPIO/TDD_FSM mux for ENABLE/TXNRX control
2015-07-01 13:52:00 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Istvan Csomortani c926daca3a ad9361/tdd: Fix generation of tx_valid_* signals
In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
2015-06-08 16:22:21 +03:00
Rejeesh Kutty 6338dfd8b7 ad9361: ip defaults & rst output 2015-06-05 09:19:39 -04:00
Istvan Csomortani 2e877389b2 ad9361_tdd: Some naming and hierarchical changes 2015-06-04 18:09:49 +03:00
Istvan Csomortani 3b1ea7e528 axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch
598ece4c8d
2015-06-04 18:09:47 +03:00
Rejeesh Kutty 2bad47cf4f delay-cntrl: up-clk, direct access + tx 2015-05-18 14:28:20 -04:00
Istvan Csomortani 2e7135c3c2 axi_ad9361_tdd: Initial commit.
Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 12:20:44 +03:00
Rejeesh Kutty 32f7e98afd ad9361: add ddr-edgesel 2015-05-06 16:58:47 -04:00
Rejeesh Kutty ee0912eb6a ad9361: make 2t2r external for mw 2015-01-05 10:54:23 -05:00
Rejeesh Kutty de33722470 up/constr: independent read/write and local constraints 2014-10-02 14:35:59 -04:00
Lars-Peter Clausen 3162540b03 axi_ad9361: Remove the Altera toplevel wrapper
By setting the AXI controler interface type from axi4 to axi4lite we can use
the normal toplevel file with only a simple modification to add the awprot
and arprot signals.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:29:13 +02:00
Lars-Peter Clausen 41cc92ef49 Remove BASEADDR/HIGHADDR parameters
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
Lars-Peter Clausen 50faf0c53a Remove executable flags from non-exectuable files 2014-09-09 15:05:06 +02:00
Rejeesh Kutty c0e31aa6c2 daq2: latest hardware 2014-07-21 09:06:57 -04:00
Rejeesh Kutty b6052773b7 added adc/dac gpio registers 2014-06-27 14:45:58 -04:00
Rejeesh Kutty 10a7804e14 ad9361: altera wrapper updates 2014-06-25 15:26:06 -04:00
Rejeesh Kutty e650253013 library: register map changes and for mathworks 2014-06-24 14:22:05 -04:00
Adrian Costina bef6a9c32c axi_ad9361: Split dma data into individual channels for both ADC and DAC 2014-06-07 17:15:31 +03:00