Commit Graph

187 Commits (25816ac1b3a0247d96646a584e49787a9a07cf5a)

Author SHA1 Message Date
Laszlo Nagy 82021edffe adi_board.tcl:ad_xcvrcon: do not reorder common control
When channels are not swapped in groups of four but are completely out of order
the common control channel can't be reordered based on the index of the
channel.
2019-11-30 12:29:32 +02:00
Adrian Costina 8c39cf8560 scripts: adi_board.tcl: Update the axi_adxcvr to util_adxcvr connections 2019-11-26 12:57:53 +02:00
Stanca Pop 40d839df5f coraz7s: Initial commit 2019-11-15 14:35:00 +02:00
Stefan Raus fd4d32c408 projects/scripts/*xilinx*: Generate report utilization extra files
Add commands to generate one extra file with resource utilization, in CSV format.
New commands executes only if ADI_GENERATE_UTILIZATION env variable is set.
2019-10-18 13:42:34 +03:00
Istvan Csomortani af94487f57 adi_project_intel: Enable HPS internal timing
It's recommended to use this global assignment so the tool can make a
more in-depth timing analysis.
2019-10-02 15:32:17 +03:00
Istvan Csomortani 75d263afc5 adi_project_xilinx: Add constraint files to constr_1 file set 2019-09-27 18:21:25 +03:00
Istvan Csomortani b174333fa2 project-xilinx.mk: Clean generated file by sysid 2019-09-27 13:16:19 +03:00
sarpadi 442b38033a sys_id: added catch to git status check
made error checking more general
2019-09-26 16:26:02 +03:00
AndreiGrozav 5e08e2d548 project-xilinx.mk: Fix build condition
"prepare_incremental_compile" is defined as a phony target, but is also a
prerequisite of a real target. This will lead to a complete project build
every time make is called.
To fix the issue the functionality of prepare_incremental_compile target
was included in the generic project build target.
2019-09-12 13:23:09 +03:00
AndreiGrozav 36a1767329 Add generic fir filters processes for RF projects 2019-08-20 16:24:47 +03:00
Sergiu Arpadi 4fe5f007cb system_id: added axi_sysid ip core and tcl 2019-08-06 16:53:11 +03:00
István Csomortáni 14a4acfd0e
projects/scripts: Fix a typo in adi_env.tcl 2019-07-25 17:58:36 +03:00
Istvan Csomortani fa610d36c6 ad_ghdl_dir: Fix global variable name
In #PR318 the global variable $ad_phdl_dir name were changed to
$ad_ghdl_dir.
2019-07-23 10:29:37 +01:00
Istvan Csomortani 6a721c0bf0 adi_env: Update system level environment variable definition
Our internal repository was changed from phdl to ghdl. Update the
adi_env.tcl scripts and other scripts, which depends on the $ad_ghdl_dir
variable. This way the tools will see all the internal IPs too.
2019-07-22 11:00:45 +03:00
Istvan Csomortani e1d9a36ae0 scripts/adi_project_intel: Rename ALT_NIOS_MMU_ENABLED to NIOS_MMU_ENABLED 2019-06-29 06:53:51 +03:00
Istvan Csomortani 363494ab9c library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 6e6f1347d7 project/scripts: Rename adi_project_alt.tcl to adi_project_intel.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani a589753d92 project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 43725429ac adi_project: Rename the process adi_project_xilinx to adi_project 2019-06-29 06:53:51 +03:00
Istvan Csomortani ec67a381e4 adi_project: Rename the process adi_project_altera to adi_project 2019-06-29 06:53:51 +03:00
Istvan Csomortani 79b6ba29ce all: Rename altera to intel 2019-06-29 06:53:51 +03:00
Istvan Csomortani 993497438b adi_project:adi_project_run: Check if $num_reg exist 2019-06-11 18:13:06 +03:00
Istvan Csomortani 896ea4925d adi_board: Fix ad_mem_hpx_interconnect proc
Make the lsearch command more robust.
2019-06-11 18:13:06 +03:00
Istvan Csomortani 20c714eccf common: Define three global clock nets
For all the Xilinx base design, define three global clock nets, which
are saved in the following three global variable: $sys_cpu_clk, $sys_dma_clk
and $sys_iodelay_clk.

These clock nets are connected to different clock sources depending of
the FPGA architecture used on the carrier. In general the following
frequencies are used:

  - sys_cpu_clk     - 100MHz
  - sys_dma_clk     - 200MHz or 250Mhz
  - sys_iodelay_clk - 200MHz or 500Mhz
2019-06-11 18:13:06 +03:00
Istvan Csomortani a7e3fcf26a adi_project_alt.tcl: Add comments to all proc 2019-05-31 10:32:40 +03:00
Istvan Csomortani 41bc947ac1 adi_project.tcl: Add comments to all proc 2019-05-31 10:32:40 +03:00
Istvan Csomortani 21031261b0 adi_board.tcl: Add comments to all proc 2019-05-31 10:32:40 +03:00
Istvan Csomortani e9a171df5f adi_board: Delete ad_reconct deprecated proc 2019-05-29 10:27:16 +03:00
Istvan Csomortani 3adefaddfd adi_xilinx_msg: New updates for 2018.3 2019-05-27 16:58:34 +03:00
Laszlo Nagy ab7ab3b32f scripts/adi_project.tcl: make search for undefined clocks more robust
Since we parse the output of a command it is likely to break in the
future if the format of the sting changes. Create a warning for that case.
2019-05-24 13:38:01 +03:00
Laszlo Nagy bf31f949e6 scripts/adi_project:adi_project_alt: add parameters to top level
Allow the top level files to have parameters.
Pass the parameters from system_project.tcl to the Vivado/Quartus project and
to the block design scripts through ad_project_params variable.

Usage:

1. create a project with a list of parameters:

adi_project_xilinx  my_project [list PARAM_A PARAM_A_VALUE PARAM_B PARAM_B_VALUE]
or
adi_project_altera  my_project [list PARAM_A PARAM_A_VALUE PARAM_B PARAM_B_VALUE]

2. access the parameter in QSYS or block design through the $ad_project_params variable

e.g
  set PARAM_A $ad_project_params(PARAM_A)
  set PARAM_B $ad_project_params(PARAM_B)

3. In system_top.v use PARAM_A and PARAM_B as parameters/generics
2019-05-24 11:05:10 +03:00
Laszlo Nagy ec636b785a scripts:adi_project.tcl: add check for missing clock definitions
Look for undefined clocks which do not show up in the timing summary
therefore can lead to silent failures.
If clocks are not defined they are not analyzed during the timing
checks.
2019-05-16 14:55:35 +03:00
Sergiu Arpadi 7ae2bc6285 adi_project: used report_timing_summary to evaluate timing 2019-05-09 12:27:35 +03:00
Sergiu Arpadi 17c20eeb7a adi_project: Fix timing check
Fixed timing paths evaluation where there is no logic in PL.
2019-05-09 12:27:35 +03:00
Laszlo Nagy 2c2be2f38a scripts: patch incremental compile
Clear the reference checkpoint if the incremental compilation is not
selected through the make option. Other case the scripts will silently
use the reference.dcp checkpoint if that exists.
2019-04-23 18:07:55 +03:00
Laszlo Nagy 525c068993 scripts: Support for incremental compilation
The scripts are looking for a previous run result, a routed design
checkpoint to use it as a reference during the incremental build flow.
Before clearing the project files, the scrips will save the reference dcp
file in the project folder.
If the reference dcp does not exists the build continues normally.

Proposed workflow:
  1. Build your project normally with 'make' or place manually a
  reference.dcp file in the Vivado project folder.
  2. Do some minor modifications
  3. Run the make with the following option:
    make MODE=incr
  4. Repeat steps 2-3
2019-04-22 10:27:16 +03:00
Laszlo Nagy 5dd9cdcdea scripts: Add common IP cache location for OOC mode
Using a common IP cache location for all the project will speed up
compile time of common blocks used in base designs. Example a MicroBlaze
core for VCU118 once compiled it will be reused on other projects.

Using a common IP cache will speed up re-compiles of every project in OOC
mode since the cache won't be cleared as with normal compile flow.
2019-04-22 10:27:16 +03:00
Laszlo Nagy 5e92dc45b2 scripts: add support for OOC synthesis flow
Usage:
from command line set any value to the ADI_USE_OOC_SYNTHESIS variable
e.g. export ADI_USE_OOC_SYNTHESIS=y
2019-04-22 10:27:16 +03:00
Adrian Costina dc5f90098e vcu118: Initial commit for common files 2019-04-17 14:24:35 +03:00
Adrian Costina 77cc0ce8ba scripts: adi_board.tcl, move from memory interconnect to smartconnect 2019-04-15 17:49:11 +03:00
AndreiGrozav e1f0b301d3 Tools version upgrade
Vivado 2018.2 -> Vivado 2018.3
Quartus 18.0  -> Quartus 18.1
2019-04-12 10:48:50 +03:00
Laszlo Nagy 8885caab13 scripts/adi_board.tcl: fix HP address mappings for ZynqMP
In the current form, when connecting a master to the HP ports all
available slave address spaces are mapped to the master (DDR_*, PCIE*, OCM,
QSPI)

Let the PL masters have access only to the DDR_LOW and DDR_HIGH address
spaces to avoid unnecessary resource usage and increase timing margin.
2019-02-27 15:04:41 +02:00
AndreiGrozav f5af939c04 Add adi make(build) scripts
adi_make.tcl
  -adi_make::lib
  -adi_make::boot_bin (executes the script adi_make_boot_bin in xsct)
adi_make_boot_bin.tcl
2018-12-11 14:02:11 +02:00
Istvan Csomortani 2b868c2857 adi_project.tcl: Update the ZCU102 board preset version 2018-10-03 15:54:29 +03:00
Lars-Peter Clausen 97409dcb88 adi_board.tcl: ad_xcvrcon: Fix width of sync port for multi-link setups
Each individual link of a multi-link has its own sync signal. The top level
sync port that is created by the ad_xcvrcon function is always a single bit
single though.

This results in only the sync signal of the first link being routed while
others are ignored.

To fix this make sure that for multi-link setups the sync port is a vector
port with the width equal to the number of links.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-09-10 13:46:38 +02:00
Istvan Csomortani 302ec5d68a adi_project_alt: Update Quartus version to 18.0.0 2018-08-23 18:41:48 +03:00
Istvan Csomortani b748488377 adi_board/adi_ip: Update Vivado version to 2018.2 2018-08-23 18:41:48 +03:00
Lars-Peter Clausen 5b94533cd0 adi_board.tcl: ad_ip_instance: Add support for specifying IP parameters
Add support for specifying a set of parameter value pairs when
instantiating an IP core to the ad_ip_instance command. This has the
convenience of not having to repeatedly call ad_ip_parameter with the name
of the core that got just created for each parameter that needs to be set.

It is also useful for cases where some parameters have mutually exclusive
values and both (or more) have to be set at the same time.

This also slightly speeds things up. Whenever a parameter is changed the
core needs to be updated and post configuration scripts might run. When
setting all parameters at the same time this only happens once instead of
once for each parameter.

For example the following sequence

  ad_ip_instance axi_dmac axi_ad9136_dma
  ad_ip_parameter axi_ad9136_dma CONFIG.DMA_TYPE_SRC 0
  ad_ip_parameter axi_ad9136_dma CONFIG.DMA_TYPE_DEST 1
  ad_ip_parameter axi_ad9136_dma CONFIG.DMA_DATA_WIDTH_SRC 64
  ad_ip_parameter axi_ad9136_dma CONFIG.DMA_DATA_WIDTH_DEST 256

can now be replaced with

  ad_ip_instance axi_dmac axi_ad9136_dma [list \
    DMA_TYPE_SRC 0 \
    DMA_TYPE_DEST 1 \
    DMA_DATA_WIDTH_SRC 64 \
    DMA_DATA_WIDTH_DEST 256 \
  ]

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-08-10 16:12:26 +02:00
AndreiGrozav ebae8bf8c1 Remove interrupts from system_top for all xilinx projects
- remove interrupts from system_top
- for all suported carriers:
	- remove all interrupt bd pins
	- connect to GND all initial unconnected interrupt pins
- update ad_cpu_interrupt procedure to disconnect a interrupt from GND
before connectiong it to another pin.
2018-08-10 10:10:58 +03:00
Istvan Csomortani e97d707f24 adi_tquest: Improve the timing report generation
If the analysis type is not defined the report_timing command will run
just a setup analysis.

Run an analysis report for all the four analysis type.
2018-08-08 15:09:19 +03:00