85f5dc8230
ad9371x/intel: Fix fPLL configuration
...
When phase alignment is active, the PFD frequency value should be used
as outclk1 actual frequency.
The configuration interface of the fPLL does not support fractional values.
If the reference clock is fractional, the tool will throw an error that requirement
above is not respected.
Round up the reference clock for the SERDES and the lane rate in order to
overcome this issue, until it's not fixed by Intel.
2021-01-12 19:34:44 +02:00
e4988aa131
adrv9371x: altera: Convert to ADI JESD204
...
Convert the ADRV9371 project for Intel/Altera platforms to the ADI JESD204
framework.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-24 17:55:10 +02:00
f278b6e6c9
adrv9371x/a10soc- constraints/project updates
2017-06-06 12:23:26 -04:00
ff7dc41066
alt-jesd- constraints update
2017-05-18 09:55:24 -04:00
ef97c1e375
adrv9371x/a10soc: Fix constraints
...
Signed-off-by: Istvan Csomortani <istvan.csomortani@analog.com>
2017-05-02 14:37:11 +03:00
b3ce821311
change pl ddr clock to 1G
2017-05-01 09:35:10 -04:00
cc6bf53d98
adrv9371x/a10soc- altera reset synchronizer false path?
2017-03-23 09:46:40 -04:00
3fa9a30f0e
a10soc/plddr4- lower mem clk to meet timing
2017-03-06 14:12:25 -05:00
bc6a09c828
adrv9371x/a10soc- dacfifo added
2017-03-01 15:35:04 -05:00
ce3b6a2d3f
adrv9371x: Updated constraints for altera projects
2016-11-04 18:20:46 +02:00
521c41ce32
adrv9371x: Updated a10soc project. Common design differentiates between nios and a10soc carrier
2016-09-08 11:44:45 +03:00
3351ff607e
adrv9371x- need to investigate merge with avalon
2016-06-02 16:22:53 -04:00
0d1c4d232e
a10soc- updates-1
2016-05-20 16:14:57 -04:00
f92e8509bb
adrv9371x- added
2016-05-20 11:46:25 -04:00
Istvan Csomortani
Lars-Peter Clausen
Rejeesh Kutty
Adrian Costina