pluto_hdl_adi

Commit Graph

Author	SHA1	Message	Date
sergiu arpadi	acbbd4636a	sysid: Upgrade framework, header/ip are now at 2/1.1.a Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl add git branch to internal use area; update log prints; update xilixn projects; fix cn0506 sysid script;	2021-01-20 01:02:56 +02:00
hotoleanudan	1c208c01d6	ad9656:Add reference design for the ad9656 eval board (#494 ) Added reference design for the ad9656 evaluation board coupled with the zcu102 carrier board. The JESD204 communication link that transfers data from the 4 ADCs to the FPGA has the following paramenters : L=4, M=4, S=1, F=2, HD=0, N=16, NP=16. The JESD204 line rate is configured to be 2.5GHz. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>	2020-10-06 09:53:40 +03:00

Author

SHA1

Message

Date

sergiu arpadi

acbbd4636a

sysid: Upgrade framework, header/ip are now at 2/1.1.a

Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;

2021-01-20 01:02:56 +02:00

hotoleanudan

1c208c01d6

ad9656:Add reference design for the ad9656 eval board (#494 )

Added reference design for the ad9656 evaluation board coupled with the
zcu102 carrier board. The JESD204 communication link that transfers data
from the 4 ADCs to the FPGA has the following paramenters : L=4, M=4, S=1,
F=2, HD=0, N=16, NP=16. The JESD204 line rate is configured to be 2.5GHz.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>

2020-10-06 09:53:40 +03:00

2 Commits (2562aead32d56eb8997e906c8c0791a793162449)