0f10623be4
AC701/VC707: Define common variables
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Define variables sys_zynq, sys_mem_size, sys_addr_cntrl_space.
2014-03-25 14:24:51 +02:00
2070c66b87
Fmcomms1: Initial commit for KC705
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Modified common project so it can be compatible for both ARM and
Microblaze based systems.
2014-03-24 16:52:24 +02:00
aa7b0bb4dd
VC707 basesys: General fixes, actual status: working
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- Add an auxiliary cpu interconnect
- Add an auxiliary interrupt concatenation module
- Add new MIG file, current frequency of the DDR interface is 100
Mhz
- Memory interconnect optimisation strategy is 'Maximize
Performance'
2014-03-24 13:07:48 +02:00
b94acf78aa
AC701 bases sys: Add an auxiliary cpu interconnect
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- Add an auxiliary cpu interconnect, the KC705 base system was
used as reference
- Base system is tested and working
2014-03-24 13:01:52 +02:00
792e8a208d
KC705 base system: Make a few cosmetic changes
2014-03-24 12:55:37 +02:00
f8c1179bc1
FMCOMMS2 KC705 Project.
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Added the files required for the FMCOMMS2 KC705 project.
Both DMA and DDS work.
2014-03-24 11:48:52 +02:00
8a08031dce
AC701: Modify interrupt concatenation
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- Interrupt concatenation is the same as in case of KC705
2014-03-24 10:20:56 +02:00
13b4dd07d0
KC705 base system: Modify interrupt concatanation
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- Add an aditional interrupt input net for the sys_concat_aux_intc
module
2014-03-21 14:45:18 +02:00
c6143dbfaf
KC705 base system: Delete trailing whitespaces.
2014-03-21 14:42:27 +02:00
31a1ff384d
FMCOMMS2 Base Design tcl modified
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Added support for both Zynq and MicroBlaze projects
2014-03-21 09:57:52 +02:00
3a0d1282b7
Fix the remaining issues
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- Swap the IO locations of ports vsync and hsync
- Change the mem_interconnect optimization strategy to Maximize
Performance
2014-03-20 14:36:01 +02:00
698e9f4757
Added phys_opt_design step for fixing timing
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The FMCOMMS1 meets timing on ZED/ZC702 only if the phys_opt_design step
is part of the implmentation flow, with the Explore argument.
"This step performs physical optimizations such as timing-driven
replicaiton of high fanouts nets to improve timing results"
2014-03-19 16:42:44 +02:00
7cdab9b5b0
Change the internal clock generator to Clock Wizard
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- Using a Clock Wizard Module, in place of the DDR Controler's MMCM for internal clock
generation.
2014-03-18 17:24:45 +02:00
9d65071235
Merge branch 'master' of https://github.com/analogdevicesinc/hdl
2014-03-18 15:30:29 +02:00
2c898bf3a2
Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project
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ZC706 runs rx_clk at 250 MHz.
ZC702 and ZED run rx_clk at 200 MHz due to slower fabric.
The ZC702 and ZED projects need init_user in the boot procedure in order for the HP Ports to work correctly.
Both DDS and DMA mode work.
2014-03-18 15:27:42 +02:00
f3c503cfb8
Merge branch 'master' of github.com:analogdevicesinc/hdl
2014-03-17 21:33:13 -04:00
dc44703cf1
zynq/non-zynq: identical signal names and instances
2014-03-17 17:02:03 -04:00
a6da4ca01c
zynq/non-zynq merge variables
2014-03-17 16:39:52 -04:00
ab8627e669
fmcomms1: Changed ILA data capture and sys constraints
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The ILA can not work at 250MHz on ZED/ZC702. Because of this, the data
path was modified from 28bits@250MHz to 56bits@125MHz, by using a FIFO.
The ZED/ZC702 max BUFG frequency is 464MHz, which corresponds to a 2.16
period so the constraints were modified accordingly.
2014-03-17 15:50:01 +02:00
ee56db8d50
FMCOMMS2: Modified FCLK2 to 125 MHz, and xdc file
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tcl: FCLK2 was modified from 100 MHz to 125 MHz.
xdc: rx_clk period constraint was redefined from 8ns (125 MHz) to 4ns (250 MHz)
2014-03-14 16:27:56 +02:00
7a6ce70e19
Fix default repository path for adi_project.tcl
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Projects can be build by running 'source system_project.tcl' in
Vivado Tcl console.
2014-03-13 10:28:16 +02:00
a6c3cb29c6
Modified SPI and ILA in fmcomms2_bd.tcl
2014-03-12 16:52:22 +02:00
92aaf0bd51
FMCOMMS1: Updated projects and axi_ad9643 core
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ZC702: Removed invalid address segments. Changed the constraints
for adc_clk to minimum possible value in order to meet timing.
ZED: Change the constraints for adc_clk to minimum possible value, in
order to meet timing
AXI_AD9643: Corrected the number of bits in the adc_mon_data bus
2014-03-12 16:23:41 +02:00
66c6b2b182
fmcomms2: added
2014-03-11 20:04:26 -04:00
f8ab734918
projects/fmcomms1: added
2014-03-11 12:16:25 -04:00
e1f23e7d49
Merge branch 'master' of github.com:analogdevicesinc/hdl
2014-03-11 09:58:34 -04:00
f3ae57a53e
global clock and reset names
2014-03-11 09:57:59 -04:00
75963ab376
Initial check in of VC707 base project
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- All source files for the VC707 base project
- Update the common base system to the new naming convention
2014-03-10 17:26:17 +02:00
793bf2f350
Change the adi_project_run process to prevent "const_type UCF" issue
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- Set the constraint type to XDC before run the synthesis
2014-03-07 11:06:11 +02:00
5c3b65d01b
adv7511: kc705/ac701 updates
2014-03-06 09:36:50 -05:00
b0a1fab743
adv7511/kc705: added
2014-03-05 10:43:16 -05:00
360f10395a
initial checkin
2014-03-03 13:42:25 -05:00
82115b138e
adv7511/ac701: initial checkin
2014-03-03 13:40:24 -05:00
c89477be5a
projects/adv7511: zynq boards
2014-03-03 10:16:49 -05:00
350ec5e633
changed path settings
2014-03-03 10:06:36 -05:00
3c0ea759a0
changed path settings
2014-03-03 10:06:02 -05:00
ddac1a8834
added common board files
2014-02-28 21:17:01 -05:00
Istvan Csomortani
Adrian Costina
ATofan
Rejeesh Kutty