Due to the delay between the dac_valid and the fifo_valid signal we need to
have two counters. One counter which counts the number of incoming
dac_valid signals and generates the dma_rd signal and one counter for the
offset which gets set to 0 when fifo_valid is set.
This fixes issues with the unpack order when only one channel is active.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This silences warnings from the tools about having no clock assigned to the bus.
Also fix the name of the TVALID signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The dummy a{r,w}len fields should have the same width as the real a{w,r}len
fields in order to not break auto AXI bus version detection.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Hide unused signals based on the number of selected channels. This silences
a few warnings from the tools about unconnected pins.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Hide unused signals based on the number of selected channels. This silences
a few warnings from the tools about unconnected pins.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When using a localparam for the width of a input/output signal the tools
won't be able to infer the size of the signal. This results in the signal
always being only 1 bit wide which causes the design to not work.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This avoids some critical warnings from Vivado that the DMA bus does not has any associated clocks.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add a helper function that can be used to register a clock and a reset interface for the clock and reset signals of a bus.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Make sure that the reference PN sequence is only incremented every two clock
cycles to make sure that it matches the rate of the ADC PN sequence.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add additional IDELAY block before the ISERDES. Delet the IDDR blocks. Be aware, the ISERDES block are running in DDR mode. If the interface is SDR the maximum parallel data width is 4.
Clear the pipeline when no transfers are active to make sure that we do not
get residual data on the first sample for the next transfer.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Always using 128bit for the input word unnecessarily increases the DMA
alignment requirements. This breaks existing software which assumes that the
DMA alignment requirement is 64bit.
So make it configurable whether we want 8 or 4 channels and while we are at
it also make the channel width configurable.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
By setting the AXI controler interface type from axi4 to axi4lite we can use
the normal toplevel file with only a simple modification to add the awprot
and arprot signals.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
We can remove the Altera toplevel wrapper if we switch the axi4 control bus
to axi4lite and add the few missing signals that are required by the Altera
interconnect to both the control and the data buses.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Make sure that if a read and a write request arrive on the very same clock
cycle to only accept one of them. The simple solution chosen here is to only
accept the write request when this happens and delay the acceptance of the
read request until the write request is finished.
This solution is not fair since a write request will always take precedence,
which in theory allows the write bus to starve the read bus. But in practice
we should never see that many write requests that we are unable to answer
the read request.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Wait for the master to accept the response for the current transaction
before we allow a new transaction to start.
This fixes problems in case the master is not ready to accept the response
when we make it available.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
We must make sure that the response ID is the same as the request ID when we
accepted the request. Otherwise we might respond with the wrong ID and the
system will lockup.
Also set rlast to 1 instead of 0.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Rejeesh Kutty
Adrian Costina
Istvan Csomortani
Lars-Peter Clausen
acozma