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2 Commits (214cf5896e52fda09c26c99632f6bfcc5087d704)

Author SHA1 Message Date
Filip Gherman 1ae375f4fb ad_quadmxfe1_ebz/vcu118: Change drp clock source used for jesd204_phy 
- Added an utility buffer in order to generate the 50Mhz DRP clock.
- 'addn_ui_clockout4' will be used to generate the higher frequency 'sys_mb' clock for Microblaze.

Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
 2022-05-27 00:48:34 +03:00
Laszlo Nagy 1cd866445e ad_quadmxfe1_ebz: Initial version 
Parametrizable project for the QUAD-MxFE platform ADQUADMXFE1EBZ,
ADQUADMXFE2EBZ, ADQUADMXFE3EBZ

Default mode set to:
  TX JESD204C MODE 11, M=16, L=4
  RX JESD204C MODE 4, M=8, L=2

For 204C 64B66B mode as physical layer the Xilinx Phy is uesd.
 2021-11-10 14:03:34 +02:00