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6 Commits (214cf5896e52fda09c26c99632f6bfcc5087d704)

Author SHA1 Message Date
Iulia Moldovan 961ebe0cc2 projects: Update .v files according to guideline 
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
 2022-06-28 18:06:56 +03:00
Laszlo Nagy 69839ec327 ad_quadmxfe1_ebz: Refactor MxFE GPIOs 2022-05-11 18:09:08 +03:00
Filip Gherman 53a95840c0 ad_quadmxfe1_ebz_bd: Bugfix for JESD configurations with less lanes 2022-05-09 10:43:31 +03:00
Filip Gherman aa1192a9bc ad_quadmxfe1_ebz_bd: Connecting all the unused lanes in util_xcvr 2022-03-23 08:13:09 +02:00
Laszlo Nagy 7702079af5 ad_quadmxfe1_ebz: Fix external sync for ADC path 2022-02-08 16:56:01 +02:00
Laszlo Nagy 1cd866445e ad_quadmxfe1_ebz: Initial version 
Parametrizable project for the QUAD-MxFE platform ADQUADMXFE1EBZ,
ADQUADMXFE2EBZ, ADQUADMXFE3EBZ

Default mode set to:
  TX JESD204C MODE 11, M=16, L=4
  RX JESD204C MODE 4, M=8, L=2

For 204C 64B66B mode as physical layer the Xilinx Phy is uesd.
 2021-11-10 14:03:34 +02:00