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11 Commits (214cf5896e52fda09c26c99632f6bfcc5087d704)

Author SHA1 Message Date
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file 
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
 2022-08-08 13:52:54 +03:00
Iulia Moldovan 961ebe0cc2 projects: Update .v files according to guideline 
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
 2022-06-28 18:06:56 +03:00
Laszlo Nagy a8174ac038 ad_quadmxfe1_ebz/vcu118/system_project.tcl: Update comments 
Update PLL selection docs.
 2022-06-08 15:35:47 +03:00
Filip Gherman 1ae375f4fb ad_quadmxfe1_ebz/vcu118: Change drp clock source used for jesd204_phy 
- Added an utility buffer in order to generate the 50Mhz DRP clock.
- 'addn_ui_clockout4' will be used to generate the higher frequency 'sys_mb' clock for Microblaze.

Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
 2022-05-27 00:48:34 +03:00
Laszlo Nagy 69839ec327 ad_quadmxfe1_ebz: Refactor MxFE GPIOs 2022-05-11 18:09:08 +03:00
Filip Gherman 53a95840c0 ad_quadmxfe1_ebz_bd: Bugfix for JESD configurations with less lanes 2022-05-09 10:43:31 +03:00
Filip Gherman aa1192a9bc ad_quadmxfe1_ebz_bd: Connecting all the unused lanes in util_xcvr 2022-03-23 08:13:09 +02:00
Laszlo Nagy 081de06ec9 ad_quadmxfe1_ebz: Update parameter description 2022-03-11 13:16:22 +02:00
Laszlo Nagy 7702079af5 ad_quadmxfe1_ebz: Fix external sync for ADC path 2022-02-08 16:56:01 +02:00
Laszlo Nagy 2386abb89c ad_quadmxfe1_ebz : Add readme file 2021-11-12 14:08:56 +02:00
Laszlo Nagy 1cd866445e ad_quadmxfe1_ebz: Initial version 
Parametrizable project for the QUAD-MxFE platform ADQUADMXFE1EBZ,
ADQUADMXFE2EBZ, ADQUADMXFE3EBZ

Default mode set to:
  TX JESD204C MODE 11, M=16, L=4
  RX JESD204C MODE 4, M=8, L=2

For 204C 64B66B mode as physical layer the Xilinx Phy is uesd.
 2021-11-10 14:03:34 +02:00