482f0489a3
scripts: Merge adi_env.tcl into a single file
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Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
961ebe0cc2
projects: Update .v files according to guideline
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Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
2a740d0c2b
ad7616_sdz: Add make env argument for interface
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Update system_project.tcl
2021-11-22 15:22:16 +02:00
591a23156b
Makefiles: Update header with the appropriate license
2021-09-16 16:50:53 +03:00
6f2f2b8626
makefile: Regenerate make files
2021-01-20 01:02:56 +02:00
acbbd4636a
sysid: Upgrade framework, header/ip are now at 2/1.1.a
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Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
9093a8c428
library: Move ad_iobuf to the common library, as it's not Xilinx specific
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Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
d8ab27b2af
sysid: Remove cstring init string
2020-09-30 19:12:24 +03:00
e7600eb552
ad7616_sdz: Fix the project, after SDI ports were merged
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Update the project to support the SDI port merge patch: 4d54c7e
2020-05-20 11:44:22 +03:00
0680e44330
system_id: deployed ip
2019-08-06 16:53:11 +03:00
5f1cb18c9b
ad7616_sdz/zc706: Fix Build
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- Fix typo
- Remove the unused(old flow) ps interupts
2019-07-10 12:51:42 +03:00
a589753d92
project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl
2019-06-29 06:53:51 +03:00
43725429ac
adi_project: Rename the process adi_project_xilinx to adi_project
2019-06-29 06:53:51 +03:00
21ce53f765
Revert "Move GTM projects to gtm_projects branch"
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This reverts commit 171093eca4
2019-06-28 11:18:29 +03:00
171093eca4
Move GTM projects to gtm_projects branch
2018-06-15 16:28:40 +03:00
377247a434
Regenerate project Makefiles using the new shared Makefile includes
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This reduces the amount of boilerplate code that is present in these
Makefiles by a lot.
It also makes it possible to update the Makefile rules in future without
having to re-generate all the Makefiles.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
425e803364
license: Fix a spelling mistake
2018-04-11 15:09:54 +03:00
a740b6012f
Make: Use $(MAKE) for recursive make commands
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This commit should resolve the issue #64 .
Recursive make commands should always use the variable MAKE, not the explicit
command name ‘make’.
2018-03-07 07:40:19 +00:00
b7ca17f02b
scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects
2017-06-07 12:06:50 +03:00
84b2ad51e2
license: Add some clarification to the header license
2017-05-31 18:18:56 +03:00
85ebd3ca01
license: Update license terms in hdl source files
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Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
9055774795
all: Update license for all hdl source files
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All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.
New license looks as follows:
Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.
Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
(at the option of the user):
1. The GNU General Public License version 2 as published by the
Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
OR
2. An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
1c23cf4621
all: Update verilog files to verilog-2001
2017-04-13 11:59:55 +03:00
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
e42b4ea378
hdlmake- updates
2016-08-04 13:28:25 -04:00
7ca8e10004
make: Update Make files
2016-08-01 14:24:48 +03:00
427cc84bb2
axi_ad7616: Rename the physical interface signals to rx_*
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No functional modification.
2016-07-01 14:45:23 +03:00
8d558b2538
make: Update Make files
2016-06-29 14:50:07 +03:00
160d54f311
ad7616_sdz: Some comment rephrase
2016-04-29 16:41:35 +03:00
1fd5c0f28b
ad7616_sdz: Fix IO definitions for the parallel interface.
2016-04-25 10:56:45 +03:00
6de356e8fc
ad7616_sdz: Fix the data width at i_iobuf_adc_cntrl
2016-04-25 10:55:37 +03:00
7ce3f6e274
ad7616_sdz: Fix system top for parallel interface mode.
2016-03-24 13:49:30 +02:00
a1c2c61884
ad7616_sdz: Update the IOBUF instance names
2016-03-24 11:46:33 +02:00
a74e2061e9
ad7616_sdz: BUSY is input for the FPGA
2016-02-03 14:12:00 +02:00
122667259f
ad7616_sdz: Update Make file
2016-01-28 14:48:44 +02:00
118577f64f
ad7616_sdz: Add support for parallel interface
2016-01-28 12:38:22 +02:00
cd43ebd8bc
axi_ad7616: The OP_MODE parameter is no longer required
2016-01-26 11:05:33 +02:00
2a17ce275c
axi_ad7616: Control inputs are controlled through GPIO
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The following control inputs are controlled through GPIO: reset_n, seq_en, hw_rngsel, chsel, crcen, burst and os.
2016-01-25 17:50:50 +02:00
14f7027793
ad7616_sdz: Move the context switching to system_project.tcl
2016-01-19 11:34:28 +02:00
17e7d1b86f
ad7616: Add Makefiles
2015-12-21 17:09:42 +02:00
ee4d5af12e
ad7616_sdz: Update the project
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+ Fix system_top.v
+ Finish up the common block design
+ Fix system_project.tcl
2015-12-14 16:02:38 +02:00
f4e3523390
ad7616_sdz: Update IO constraints
2015-12-14 15:34:56 +02:00
214adbfd85
ad7616_sdz_zc706: Add board related IO's to system top.
2015-11-09 10:51:46 +02:00
27266c59ee
ad7616_sdz: Add project source files
2015-11-03 15:03:35 +02:00
Iacob_Liviu
Iulia Moldovan
Stanca Pop
Adrian Costina
Sergiu Arpadi
Istvan Csomortani
AndreiGrozav
Lars-Peter Clausen
Rejeesh Kutty