482f0489a3
scripts: Merge adi_env.tcl into a single file
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Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
961ebe0cc2
projects: Update .v files according to guideline
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Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
591a23156b
Makefiles: Update header with the appropriate license
2021-09-16 16:50:53 +03:00
7b7609d21a
ad469x: Clean system_project.tcl
2021-06-03 15:41:58 +03:00
6a374ef457
ad469x/zed: Add multicycle path constraint
2021-03-22 13:05:05 +02:00
acbbd4636a
sysid: Upgrade framework, header/ip are now at 2/1.1.a
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Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
9093a8c428
library: Move ad_iobuf to the common library, as it's not Xilinx specific
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Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
7cc5716ea8
ad469x: Remove sysid custom string init
2020-10-28 11:31:50 +02:00
35e4eb6a7b
ad469x: Add reference design for ad469x eval board
2020-10-22 19:17:10 +03:00
Iacob_Liviu
Iulia Moldovan
Adrian Costina
sergiu arpadi