Commit Graph

8 Commits (214cf5896e52fda09c26c99632f6bfcc5087d704)

Author SHA1 Message Date
Iulia Moldovan 0c0617d49e libraries: Update modules according to guideline
* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
alin724 e61cadb2ca axi_dmac: Restore axi_dmac_regmap_request to f7b8a2d version 2021-07-02 15:52:48 +03:00
Alin-Tudor Sferle 54c65013aa
Fix registers mismatches in regmap_tb from jesd 204 rx/tx and dmac
* dmac_tb: Fix regmap_tb registers mismatches

* jesd204: Fix jes204 rx and tx regmap_tb Octets per multiframe mismatch
2021-05-31 16:47:12 +03:00
stefan.raus 37238916df Testbenches: Unify and optimize HDL testbenches
Create a common 'run_tb.sh' script to be called by every testbench.
Unify file and testbenches names.
Fix util_pack/cpack_tb.
Add parameters '-batch' and '-gui' for modelsim and xsim simulators (default is gui)
Add ascript for that generates output in xml format (used by CI tools).
2021-05-07 19:53:14 +03:00
Laszlo Nagy 20ac7dcaef axi_dmac: component level testbench updates 2018-09-07 11:38:04 +03:00
Lars-Peter Clausen 8ddcffcafc axi_dmac: Enforce transfer length and stride alignments
In its current implementation the DMAC requires that the length of a
transfer is aligned to the widest interface. E.g. if the widest interface
is 128 bits wide the length of the transfer needs to be a multiple of 16
bytes.

If the requested length is not aligned to the interface width it will be
rounded up.

This works fine as long as both interfaces have the same width. If they
have different widths it is possible that the length is rounded up to
different values on the source and destination side. In that case the DMA
will deadlock because the transfer lengths don't match and either not enough
of too much data is delivered from the source to the destination side.

Currently it is up to software to make sure that such an invalid
configuration is not possible.

Also enforce this requirement in the DMAC itself by setting the LSBs of the
transfer length to a fixed 1 so that the length is always aligned to the
widest interface.

Software can also use this to discover the length alignment requirement, by
first writing a zero to the length register and then reading the register
back. The LSBs of the read back value will be non-zero indicating the
alignment requirement.

In a similar way the stride needs to be aligned to the width of its
respective interface, so the generated addresses stay aligned. Enforce this
in the same way by keeping the LSBs cleared.

Increment the minor version number to reflect these changes.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-03 13:44:34 +02:00
Laszlo Nagy ee4932ecee axi_dmac: made vlog pass
Did minor changes to the code to make ModelSim vlog pass.
2018-05-03 14:49:06 +02:00
Lars-Peter Clausen b3f027fc89 axi_dmac: Add simple register map testbench
Add a testbench that exercises the basic functionality of the axi_dmac
register map module.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-03 14:49:06 +02:00