Commit Graph

14 Commits (213e852e11461cdad31d1771414087ae3f0a127b)

Author SHA1 Message Date
Istvan Csomortani 179d6d601c adi_board.tcl : Use 'global' instead of '$::' 2014-04-14 11:45:35 +03:00
Istvan Csomortani c718169f27 adi_board.tcl : Fix the address assignment command
A lot of cores have more than one address segments, therefor need
	to filter out the segment of the axi lite interface
2014-04-11 16:14:56 +03:00
Istvan Csomortani cf5b9b51fd adi_board.tcl : Fix spi ports and hp clocks 2014-04-11 15:31:12 +03:00
Istvan Csomortani 37e2059fd0 adi_board.tcl : General update
- Split the adi_dma_interconnect to two procedure:
	  adi_dma_interconnect and adi_hp_assign
	- Fix the adi_spi_core
	- Fix the adi_interconnect_lite
2014-04-10 18:29:14 +03:00
Istvan Csomortani 5b0e37b97a adi_project.tcl : Modify implementation strategy
- Change implementation strategy to Performance Explore.
	  At some projects, this could prevent timing issues, it not
	  increase the overall implementation time in a dramatic way.
2014-04-07 15:02:38 +03:00
Istvan Csomortani 8deb36ce08 adi_board.tcl: All procedures works on Zynq/Microblaze
General patch for the integration procedures. Tested on kc705 and
	zed.
2014-04-01 16:19:24 +03:00
Istvan Csomortani 4ef88a3bed adi_board.tcl : Patch for adi_spi_core process
- Fix indentation
	- Pacth for adi_spi_core process
2014-03-31 16:41:07 +03:00
Istvan Csomortani 7f4f200fce Project scripts: Initial check in of adi_board.tcl
The script contains integration tcl processes.
2014-03-26 19:08:56 +02:00
Adrian Costina 698e9f4757 Added phys_opt_design step for fixing timing
The FMCOMMS1 meets timing on ZED/ZC702 only if the phys_opt_design step
is part of the implmentation flow, with the Explore argument.
"This step performs physical optimizations such as timing-driven
replicaiton of high fanouts nets to improve timing results"
2014-03-19 16:42:44 +02:00
Istvan Csomortani 7a6ce70e19 Fix default repository path for adi_project.tcl
Projects can be build by running 'source system_project.tcl' in
	Vivado Tcl console.
2014-03-13 10:28:16 +02:00
Rejeesh Kutty f3ae57a53e global clock and reset names 2014-03-11 09:57:59 -04:00
Istvan Csomortani 793bf2f350 Change the adi_project_run process to prevent "const_type UCF" issue
- Set the constraint type to XDC before run the synthesis
2014-03-07 11:06:11 +02:00
Rejeesh Kutty 350ec5e633 changed path settings 2014-03-03 10:06:36 -05:00
Rejeesh Kutty ddac1a8834 added common board files 2014-02-28 21:17:01 -05:00