3c6c45962a
adrv9371x/kcu105: Hook up un-gated ref clock to fabric
2022-02-15 11:09:37 +02:00
572005abe4
adrv9371x/zcu102: Hook up un-gated ref clock to fabric
2022-02-15 11:09:37 +02:00
501903bc81
adrv9371x/zc706: Hook up un-gated ref clock to fabric
2022-02-15 11:09:37 +02:00
39e073e6bf
adrv9371x: Use the output of IBUFDS_GTE2 as reference for the clock gens
...
In some cases (GTX2) the transceiver may gate the out_clk when it is in
reset. This will stop the clock generators from getting a clock prior
removing the reset of the XCVR. The XCVR has a requirement of running
user clock while removing the reset. The correct sequence must be :
Enable device clocks (user clock)
Remove the reset from the XCVR
2022-02-15 11:09:37 +02:00
86d754ae85
projects/scripts: Add gtwizard scripts
2022-02-14 10:32:58 +02:00
62dc310794
Revert "intel: Update projects to use ad_iobuf instead of ALT_IOBUF"
...
This reverts commit a3a610728c
2022-02-09 17:39:29 +02:00
4790d334ad
dac_fmc_ebz: NUM_LINKS added to system_top.v
2022-02-09 12:23:12 +02:00
7702079af5
ad_quadmxfe1_ebz: Fix external sync for ADC path
2022-02-08 16:56:01 +02:00
3ff2887485
dac_fmc_ebz_vcu118: Initial commit
2022-02-08 14:34:47 +02:00
694ebbfbfc
dac_fmc_ebz_bd.tcl: Updated bd for multiple tx_ref_clk
2022-02-08 14:34:17 +02:00
45dae0f3d3
ad9081_fmca_ebz/common: Connect sync at TPL level
...
Reset CPACK from ADC TPL so during armed capture clear the cpack to avoid
capturing old samples.
Reset UNPACK with TPL to clear upack during armed transfers to avoid
sending old data.
2022-02-07 19:14:01 +02:00
8ec657315c
adrv9009zu11eg: Drive cpack/upack reset from TPL
2022-02-07 19:14:01 +02:00
d949936a1b
adrv9009zu11eg/common: EXT_SYNC updates
...
- Explicitly enable EXT_SYNC parameter for Rx/Obs
- Loopback manual sync for each TPL (we do not combine them yet because
it requires extra CDC logic)
2022-02-07 19:14:01 +02:00
63a1233101
ad7134_fmc: Update Readme
2022-02-07 14:41:25 +02:00
4827e5eb18
ad7134_fmc: Switch offload trigger to falling ODR
2022-02-07 14:41:25 +02:00
297bed6721
ad7134_fmc: Change ODR signal to output
...
FPGA is now generating the ODR signal using axi_pwm_gen.
Both ADCs are now in slave mode.
2022-02-07 14:41:25 +02:00
b63ebca292
projects/cn0506_rmii/*: Add util_mii_to_rmii library to project
2022-02-03 10:23:12 +02:00
3da9d9fcb4
pluto_ng: Initial commit
2022-02-03 09:56:13 +02:00
7dae0858b0
de10nano: changed quartus version to 20.1.1
2022-01-31 14:10:51 +02:00
bc5974d789
ad77681evb: Fix irq overlap
...
spi engine irq signal was overwriting fmc iic irq
2022-01-31 12:32:31 +02:00
f34b561e19
daq3: Parameterize JESD204 configuration values
...
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-31 10:47:01 +02:00
e8ff32d6df
ad6676evb: Parameterize JESD204 configuration values
...
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-31 10:36:31 +02:00
318523579f
ad6676evb: Update to JESD204 TPL instantiation
...
Updated the JESD204 TPL instantation of the design.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-31 10:36:31 +02:00
9ca5ae07b2
ad9783: Add Readme.md
2022-01-25 17:16:30 +02:00
530aca9754
daq2: Parameterize JESD204 configuration values
...
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-20 12:54:03 +02:00
f3cf7508c8
ad9783: Update Makefile
2022-01-20 12:31:57 +02:00
4ec8797c7c
adrv9009: Parameterize JESD204 configuration values
2022-01-13 10:15:05 +02:00
6a92bd5925
adrv9371x: Parameterize JESD204 configuration values
2022-01-12 16:05:48 +02:00
d8a418d8d0
projects/scripts/adi_board/tcl: Updated ad_xcvrcon procedure for parametrized projects
2022-01-12 16:05:18 +02:00
fc04198b2b
adrc9361_ccfmc: Fix SFP pin locations
2022-01-12 13:43:06 +02:00
86d2467f57
fmcjesdadc1: Parameterize JESD204 configuration values
...
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-12 13:28:42 +02:00
3d000ee6a8
ad9783_zcu102_dev: Initial commit
2022-01-07 14:04:08 +02:00
6dddaaaa78
adrv9009zu11eg/adrv2crr_xmicrowave: Update Makefile
2021-12-22 11:33:15 +02:00
0d45f4dc94
xmicrowave: Fix typo
2021-12-17 15:44:23 +02:00
38c489d254
projects: set Quartus version for cyclone5, cn0506_mii and cn0506_rgmii
2021-12-15 17:13:38 +02:00
fb17147eb4
fmcadc2: Parameterize JESD204 configuration values
...
Add the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-10 20:54:39 +02:00
13a282d9c4
fmcadc2: Update JESD204 TPL instance
...
Updated the JESD204B transport layer instance to instantiate the new TPL IP
module.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-10 20:54:39 +02:00
77f3e5155b
ad9081_fmca_ebz: Fix signal length parameter
...
Corrected the length parameter for the rx_data input.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-08 14:29:48 +02:00
1b8ca5f045
fmcjesdadc1: bd: Clean trailing white spaces and alignment
...
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-12-03 16:10:51 +02:00
8e226282cd
fmcjesdadc1: bd: Replace hardcoded lane number with parameter
...
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-12-03 16:10:51 +02:00
80b3fc2d0a
ad9081_fmca_ebz: versal: Remove unused GT reset input pin
...
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-22 16:18:29 +02:00
1ec0993d33
ad9081_fmca_ebz/vcu128: Remove ref clock replica
...
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-22 16:18:29 +02:00
2a740d0c2b
ad7616_sdz: Add make env argument for interface
...
Update system_project.tcl
2021-11-22 15:22:16 +02:00
c2d37b2db3
pulsar_adc_pmdz: Initial commit
2021-11-22 13:39:17 +02:00
c71e5de928
zcu102: ad_fmclidar1_ebz, fmcomms5, fmcomms8 ( #811 )
...
adrv2crr_fmc: adrv9009zu11eg
adrv2crr_xmicrowave: adrv9009zu11eg
The IBUFGDS primitive is deprecated in UltraScale devices.
2021-11-22 08:09:46 +02:00
3cd203e9c7
scripts/adi_board.tcl: improvements for vcu128 DDR controller
...
- allow specifying the name of Axi Lite interface from the peripheral were to connect the control bus
- some DDR controllers have an Axi Lite control interface, this creates
a second address segment which causes issues, differentiate the memory
segment from control registers segment
2021-11-19 18:08:16 +02:00
e76f287e73
ad9081_fmca_ebz:vcu128: Initial version
...
* 4Txs / 4Rxs per MxFE
* Tx I/Q Rate: 250 MSPS
* Rx I/Q Rate: 250 MSPS
* DAC JESD204B: Mode 9, L=4, M=8, N=N'=16
* ADC JESD204B: Mode 10, L=4, M=8, N=N'=16
* DAC-Side JESD204B Lane Rate: 10Gbps
* ADC-Side JESD204B Lane Rate: 10Gbps
2021-11-19 18:08:16 +02:00
88b5c2d6db
projects/common/vcu128: Initial VCU128 support
2021-11-19 18:08:16 +02:00
e00def31d0
ad9081_fmca_ebz: versal: Remove external gt_reset logic
2021-11-19 14:01:48 +02:00
0b9631f1f7
ad9081_fmca_ebz: versal: Rename nets
2021-11-19 14:01:48 +02:00
ca6248ba88
ad9081_fmca_ebz/common/versal_transceiver.tcl: Reset also PLL
2021-11-19 14:01:48 +02:00
731ed0a7a5
ad9081_fmca_ebz/vck190: Updated to hierarchical versal transceiver
...
Vivado cannot nest multiple block designs than two layers. This makes
replication of designs difficult.
Create a hierarchy around the Versal transceiver that includes also the
converters, this type of interface would match the util_adxcvr
interface.
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-19 14:01:48 +02:00
1d951cfbae
ad9081_fmca_ebz/vck190: Change default profile to 2 lanes
2021-11-19 14:01:48 +02:00
81c7d7475d
ad463x: Fix readme
2021-11-17 16:48:59 +02:00
5795cf6720
ad9213_dual_ebz: Readme.md : Remove incorrect product page
2021-11-15 13:59:26 +02:00
daba543797
ad9082_fmca_ebz: Readme.md: Remove AD9081 from parts
2021-11-15 13:59:26 +02:00
fe9afd4392
ad9208_dual_ebz: Readme.md: Remove invalid product page
...
Product page on analog.com does not exists
2021-11-15 13:59:26 +02:00
2386abb89c
ad_quadmxfe1_ebz : Add readme file
2021-11-12 14:08:56 +02:00
adad6c930d
ad9081_fmca_ebz_qsys.tcl: Add RX_LANE_RATE and TX_LANE_RATE parameters
...
For ad9081/a10soc project, the RX_LANE_RATE and TX_LANE_RATE were computed
from SAMPLE_RATE. Remove SAMPLE_RATE and add RX_LANE_RATE and TX_LANE_RATE
as parameters. Update also computation examples from comments.
Signed-off-by: stefan.raus <stefan.raus@analog.com>
2021-11-12 13:04:57 +02:00
fe58a5fb47
adrv9009zu11eg/adrv2crr_fmcomms8: Add clock buffers for core clocks
...
The IBUFGDS primitive is deprecated in UltraScale devices.
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-11 17:33:10 +02:00
1cd866445e
ad_quadmxfe1_ebz: Initial version
...
Parametrizable project for the QUAD-MxFE platform ADQUADMXFE1EBZ,
ADQUADMXFE2EBZ, ADQUADMXFE3EBZ
Default mode set to:
TX JESD204C MODE 11, M=16, L=4
RX JESD204C MODE 4, M=8, L=2
For 204C 64B66B mode as physical layer the Xilinx Phy is uesd.
2021-11-10 14:03:34 +02:00
63b6711cfa
start adding some doc to the ./projects directory
...
This adds a Readme.md to each project directory with pointers to project
documentation in the wiki, and the drivers (if they exist). This will
help with some autogenerated doc in the wiki, that is generated with the
innovatily named "wiki_summary.sh" shell script that parses through
these Readme.md files, and generates a summary table.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Iacob Liviu Mihai <liviu.iacob@analog.com>
2021-11-10 14:01:06 +02:00
58c1d2e3b2
projects: fixed xcvr clocks that generated critical warning
2021-11-09 12:40:14 +02:00
5ad40b29e5
adrv9001/zed: Use global clock buffers for better fit the design
...
Occasionally with zed, the implementation failed at the placement stage where
the tool could not fit the logic cells inside a single clock region,
constraint required by the usage of regional clock buffers.
This commit allows the usage of the global clock buffers which help the tool
in such cases and allow a larger application logic to be implemented in fabric.
2021-11-08 13:53:51 +02:00
457c5f7d86
fmcjesdadc1: Fix ad9250 core parameters settings
...
Fix CONVERTER_RESOLUTION parameter setting for ad9250. Also deleted the
setting of BITS_PER_SAMPLE and DMA_BITS_PER_SAMPLE for ad9250 since they
are set by default to the desired values.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-11-04 12:18:06 +02:00
bcf5abb2fe
xmicrowave: Initial commit
2021-11-02 15:44:47 +02:00
1bc8a41aea
vc709_carrier: Add vc709 carrier ( #788 )
...
Added vc709 carrier to the projects/common folder location.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-11-02 12:05:42 +02:00
c5d216bba9
adrv9001/zcu102: Enable independent TX mode in CMOS
...
For CMOS case, lane rates are so low that reference clock of the source
synchronous interface can be routed on non-clock routes. The delays on
the clock line are adjusted by the digital interface tuning controlled
through software.
Lock down clock buffers on Rx and Tx interfaces, this avoids suboptimal
placement which causes large skew between clocks at the serdes pins.
2021-10-27 14:40:08 +03:00
03682f6193
projects/adrv9001/zcu102/lvds_constr.xdc: Fix timing constraints
...
1. Reduce max allowed skew between source synchronous clocks that can
occur due PCB differences. 250ps represents a difference more than an
inch.
2. In order to reduce skew between source synchronous clock and the
divided clock instruct the tool to use a common clock root for them.
2021-10-27 14:40:08 +03:00
d4126739b4
projects: remove hardcoded div_clk from xcvr
2021-10-27 12:11:22 +03:00
cb861f5299
ad463x: Fix readme
2021-10-26 15:42:57 +03:00
15a6480601
ad4630_fmc: Initial commit
2021-10-18 16:13:31 +03:00
ff090b60ef
daq2/zcu102: Fix the ad9144 data offload to use internal BRAM
2021-10-15 15:03:22 +03:00
3640c2b584
daq2/kcu105: Fix the ad9144 data offload to use internal BRAM
2021-10-15 15:03:22 +03:00
6ad54c1056
daq2/kc705: Fix the ad9144 data offload to use internal bram
2021-10-15 15:03:22 +03:00
907cd613aa
daq2/zc706: Increase BRAM utilization to 52%
2021-10-15 15:03:22 +03:00
e34346360d
scripts: Add logic for vivado version check
2021-10-12 14:34:11 +03:00
5db7574dce
scripts/adi_board.tcl: For older families stick with axi_interconnect
...
SmartConnect has higher resource utilization and worse timing closure
that makes several zed based projects to fail timing.
2021-10-07 14:18:49 +03:00
9295218a64
projects/ad9081_fmca_ebz: Updated makefiles
2021-10-05 16:56:57 +03:00
51b643b978
Makefile: Fix misc makefiles from projects and library
2021-10-05 14:24:48 +03:00
3a1babe366
ad9081_fmca_ebz/vck190: Reset GT with HMC7044 lock
...
Reset transceiver with a pulse
2021-10-05 14:09:51 +03:00
2562aead32
ad9081_fmca_ebz/common: Drive Rx DMA system side with DMA clock
2021-10-05 14:09:51 +03:00
8d547f31e1
ad9081_fmca_ebz/vck190: Initial version
2021-10-05 14:09:51 +03:00
6c58a8d1ab
ad9081_fmca_ebz/common: Add Versal transceiver support
2021-10-05 14:09:51 +03:00
56a25afa68
common/vck190: Initial version
2021-10-05 14:09:51 +03:00
6a681b9e8d
common/vmk180_es1: Initial version
2021-10-05 14:09:51 +03:00
833e5f0aff
common/vmk180: Initial version
2021-10-05 14:09:51 +03:00
2fec1356d6
scripts/adi_project_xilinx.tcl: VCK190 support
2021-10-05 14:09:51 +03:00
222c5782b6
scripts/adi_project_xilinx.tcl: Install ES1 board from XHUB, make project compile in batch mode
2021-10-05 14:09:51 +03:00
011c8c1f36
scripts/adi_project_xilinx.tcl: Add VMK180 & VMK180_ES1 support
2021-10-05 14:09:51 +03:00
c22f622599
scripts/adi_board.tcl: Versal support for memory interconnect and irq interconnect
2021-10-05 14:09:51 +03:00
08c2ce75fe
scripts/adi_board.tcl: Switch cpu_interconnect to SmartConnect
2021-10-05 14:09:51 +03:00
aaaba50f83
scripts/project-xilinx.mk: Update target to xsa and cleanup list
2021-10-05 14:09:51 +03:00
0a986f76b8
scripts: QUARTUS_VERSION and PRO_ISUSED can be set in system_project.tcl
2021-10-02 12:34:10 +03:00
0a3724e04c
s10soc: Update base desgin from ES to production, H-Tile version
2021-09-30 17:40:13 +03:00
5a3c3c878b
ad9213_dual_ebz: Initial commit
...
Used ADF4377 SPI configuration CPOL/CPHA 1 for increasing the reliability of the level translators
ad9213_dual_ebz/s10soc: Redesign the address layout
avl_peripheral_mm_bridge 0x0000000 0x0001FFFF
* sys_gpio_in 0x00000000
* sys_gpio_out 0x00000020
* sys_spi 0x00000040
* sys_gpio_bd 0x000000D0
* sys_id 0x000000E0
avl_mm_bridge_0 0x00040000 0x0007FFFF
* ad9213_rx_0.phy_reconfig_0 0x00000000
* ad9213_rx_0.phy_reconfig_1 0x00002000
* ad9213_rx_0.phy_reconfig_2 0x00004000
* ad9213_rx_0.phy_reconfig_3 0x00006000
* ad9213_rx_0.phy_reconfig_4 0x00008000
* ad9213_rx_0.phy_reconfig_5 0x0000A000
* ad9213_rx_0.phy_reconfig_6 0x0000C000
* ad9213_rx_0.phy_reconfig_7 0x0000E000
* ad9213_rx_0.phy_reconfig_8 0x00010000
* ad9213_rx_0.phy_reconfig_9 0x00012000
* ad9213_rx_0.phy_reconfig_10 0x00014000
* ad9213_rx_0.phy_reconfig_11 0x00016000
* ad9213_rx_0.phy_reconfig_12 0x00018000
* ad9213_rx_0.phy_reconfig_13 0x0001A000
* ad9213_rx_0.phy_reconfig_14 0x0001C000
* ad9213_rx_0.phy_reconfig_15 0x0001E000
* ad9213_rx_0.link_pll_reconfig 0x00020000
avl_mm_bridge_1 0x00080000 0x000BFFFF
* ad9213_rx_1.phy_reconfig_0 0x00000000
* ad9213_rx_1.phy_reconfig_1 0x00002000
* ad9213_rx_1.phy_reconfig_2 0x00004000
* ad9213_rx_1.phy_reconfig_3 0x00006000
* ad9213_rx_1.phy_reconfig_4 0x00008000
* ad9213_rx_1.phy_reconfig_5 0x0000A000
* ad9213_rx_1.phy_reconfig_6 0x0000C000
* ad9213_rx_1.phy_reconfig_7 0x0000E000
* ad9213_rx_1.phy_reconfig_8 0x00010000
* ad9213_rx_1.phy_reconfig_9 0x00012000
* ad9213_rx_1.phy_reconfig_10 0x00014000
* ad9213_rx_1.phy_reconfig_11 0x00016000
* ad9213_rx_1.phy_reconfig_12 0x00018000
* ad9213_rx_1.phy_reconfig_13 0x0001A000
* ad9213_rx_1.phy_reconfig_14 0x0001C000
* ad9213_rx_1.phy_reconfig_15 0x0001E000
* ad9213_rx_1.link_pll_reconfig 0x00020000
Connected directly to the h2s_lw_axi_master
* ad9213_rx_0.link_reconfig 0x000C0000
* ad9213_rx_0.link_management 0x000C4000
* ad9213_rx_1.link_reconfig 0x000C8000
* ad9213_rx_1.link_management 0x000CC000
* axi_ad9213_0.s_axi 0x000D0000
* axi_ad9213_1.s_axi 0x000D1000
* axi_ad9213_dma_0.s_axi 0x000D2000
* axi_ad9213_dma_1.s_axi 0x000D3800
2021-09-30 17:40:13 +03:00
8acf0296af
s10soc:ad_cpu_interconnect: Add an avl_address_width attribute
...
The default address space for a new bridge is 256 Kbytes. Add an
avl_address_width attribute to the ad_cpu_interoconnect porecess to
define other address space sizes if needed.
The avl_peripheral_mm_bridge will have an 128 Kbyte address space from
address 0x0000.
2021-09-30 17:40:13 +03:00
edd2956d58
data_offload: Fix util_[cu]pack offset to TDD syncs
...
Signed-off-by: David Winter <david.winter@analog.com>
2021-09-30 14:45:54 +03:00
b9554a9a5a
ad9081_fmca_ebz: Integrate axi_tdd into zcu102 design
...
Signed-off-by: David Winter <david.winter@analog.com>
2021-09-30 14:45:54 +03:00
58737e09ba
adi_project_intel.tcl: update quartus to 21.2
...
Update Quartus version to 21.2.0.
Signed-off-by: stefan.raus <stefan.raus@analog.com>
2021-09-30 09:53:53 +03:00
Laszlo Nagy
LIacob106
Adrian Costina
Filip Gherman
sergiu arpadi
alin724
AndreiGrozav
Dan Hotoleanu
Iulia Moldovan
Stanca Pop
PopPaul2021
Laszlo Nagy
stefan.raus
Robin Getz
hotoleanudan
Istvan Csomortani
Mihaita Nagy
David Winter