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16 Commits (20b89ddd99d1619d68959889a0208cd62f02e6d8)

Author SHA1 Message Date
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
Sergiu Arpadi 6f2f2b8626 makefile: Regenerate make files 2021-01-20 01:02:56 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a 
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
 2021-01-20 01:02:56 +02:00
Istvan Csomortani 37254358dd makefile: Regenerate make files 2020-10-20 12:51:10 +03:00
Sergiu Arpadi d8ab27b2af sysid: Remove cstring init string 2020-09-30 19:12:24 +03:00
Sergiu Arpadi 3241924d14 sysid_intel: Added sysid to intel projects 2020-09-11 15:46:06 +03:00
Istvan Csomortani 4684dc03ce dac_fmc_ebz/a10soc: Use balanced optimization mode 
Always a good idea to start from default, and change optimization mode
of the tool if it's strict necessary.
 2020-03-17 17:25:02 +00:00
Istvan Csomortani 253a8cb6ee dac_fmc_ebz/a10soc: Tool expect that all config parameters exists on top entity 2020-03-17 17:25:02 +00:00
Laszlo Nagy 35412c81a9 dac_fmc_ebz: drive spi_en pin automatically based on FMC board selected 
spi_en is active ...
   ... high for AD9135-FMC-EBZ, AD9136-FMC-EBZ, AD9144-FMC-EBZ,
   ... low for AD9171-FMC-EBZ, AD9172-FMC-EBZ, AD9173-FMC-EBZ
 2020-03-03 15:49:30 +02:00
Istvan Csomortani aa5fdf903e Makefile: Update makefiles 2019-08-26 16:58:01 +03:00
Istvan Csomortani 5329458a62 library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani ec67a381e4 adi_project: Rename the process adi_project_altera to adi_project 2019-06-29 06:53:51 +03:00
Istvan Csomortani 79b6ba29ce all: Rename altera to intel 2019-06-29 06:53:51 +03:00
Laszlo Nagy 3bf120123b dac_fmc_ebz: update Makefiles 2019-06-06 11:45:05 +03:00
Laszlo Nagy 1541b918d8 dac_fmc_ebz: added README 2019-06-06 11:45:05 +03:00
Lars-Peter Clausen 6d31a437aa dac_fmc_ebz: Add initial Arria10 SoC support 
Add support for the Arria 10 SoC development kit to the dac_fmc_ebz
project.

This allows to use the following FMC boards on the Arria 10 SoC development
Kit carrier:
  * AD9135-FMC-EBZ
  * AD9136-FMC-EBZ
  * AD9144-FMC-EBZ
  * AD9152-FMC-EBZ
  * AD9154-FMC-EBZ
  * AD9171-FMC-EBZ
  * AD9172-FMC-EBZ
  * AD9173-FMC-EBZ

Note that the board in its default configuration is not fully compatible with the
mentioned FMC boards and some slight re-work moving some 0 Ohm resistors is
required. The rework concerns the LA01 and LA05 pins, which by default are
not connected to the FPGA. The changes required are:

  LA01_P_CC
    R612: R0 -> DNI
    R610: DNI -> R0
  LA01_N_CC
    R613: R0 -> DNI
    R611: DNI -> R0
  LA05_P
    R621: R0 -> DNI
    R620: DNI -> R0
  LA05_N
    R633: R0 -> DNI
    R632: DNI -> R0

The main differences between AD9144-FMC-EBZ and AD9172-FMC-EBZ are:
  * The DAC txen signals are connected to different pins
  * The polarity of the spi_en signal is active low instead of active high
  * The maximum lane rate is up to 15.4 Gpbs

To accommodate this all 4 possible txen signals as well as the spi_en
signal are connected to GPIOs. Software can decide how to use them
depending on which FMC board is connected.

Note that each carrier has a maximum supported lane rate. Modes of the
AD9172 (and similar) that exceed the carrier specific limit can not be used
on that carrier. The limits are as following:
  * A10SoC: 14.2 Gbps
 2019-06-06 11:45:05 +03:00