ab5c344c89
ad_fmclidar1_ebz:a10soc Fixed SPI communication on Arria 10 ( #947 )
...
Signed-off-by: Liviu Adace <liviu.adace@analog.com>
2022-05-24 12:44:03 +03:00
62dc310794
Revert "intel: Update projects to use ad_iobuf instead of ALT_IOBUF"
...
This reverts commit a3a610728c
2022-02-09 17:39:29 +02:00
591a23156b
Makefiles: Update header with the appropriate license
2021-09-16 16:50:53 +03:00
6f2f2b8626
makefile: Regenerate make files
2021-01-20 01:02:56 +02:00
acbbd4636a
sysid: Upgrade framework, header/ip are now at 2/1.1.a
...
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
685ca91f19
ad_fmclidar1_ebz/a10soc: Fix a typo
...
Fixing a typo in projects/ad_fmclidar1_ebz/a10soc/system_top.v.
2020-11-05 12:53:50 +02:00
a3a610728c
intel: Update projects to use ad_iobuf instead of ALT_IOBUF
2020-11-02 16:13:35 +02:00
37254358dd
makefile: Regenerate make files
2020-10-20 12:51:10 +03:00
d8ab27b2af
sysid: Remove cstring init string
2020-09-30 19:12:24 +03:00
3241924d14
sysid_intel: Added sysid to intel projects
2020-09-11 15:46:06 +03:00
32eeedb660
makefile: Update makefiles
2020-05-07 08:41:49 +01:00
522aacf6d8
ad_fmclidar1_ebz/a10soc: Fix AFE's I2C interface
...
The AFE's I2C interface should be pin-multiplexed to the FPGA. Also, add
a bidirectional IO buffer for the interface, and make sure it has weak
pull-up resistors.
2020-03-17 07:27:49 +00:00
b3e475cb8b
ad_fmclidar1_ebz: Update the IO constraints to revB
...
The IO location of the laser_driver_otw_n was moved from FMC_HPC_LA27_N
to FMC_HPC_LA31 (laser_gpio[12]).
laser_gpio[11:0] assignments were shifted with one bit to MSB, and laser_gpio[0]
got the old location of the laser_driver_otw_n.
2020-01-31 18:47:37 +02:00
03bec4b49c
ad_fmclidar1_ebz: Interchange SYSREF and DEV_CLK ports location
...
In ZCU102 LA01_CC_P|N are connected to regional clock, but in order to
receive a device clock properly we have to use pin which is connected
to a global clock buffer. Luckily SYSREF is connected to global clock
pin; swap to port to receive the device clock correctly.
Also, swap the ports in both ZC706 and A10SOC carriers.
2019-10-17 09:59:23 +03:00
3084a5d9aa
ad_fmclidar1_ebz/a10soc: Fix the comment about the carrier re-work
...
The project is using the FMCA connector of the board. Make sure that all
the carrier re-work is related to the FMCA connector.
2019-10-17 09:58:52 +03:00
2344778dd8
ad_fmclidar1_ebz/a10soc: Initial commit
...
Add initial support for Arria 10 SOC carrier.
2019-10-02 15:32:17 +03:00
ladace
Adrian Costina
Sergiu Arpadi
stefan.raus
Istvan Csomortani