Istvan Csomortani
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7960b00684
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block_design: Update with new clock net variables
Using the new clock net variables in all Xilinx block designs.
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2019-06-11 18:13:06 +03:00 |
AndreiGrozav
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d894c30c2d
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Remove deprecated/unused parameters
adrv9009
adrv9371x
arradio
daq2
daq3
fmcomms2
fmcomms5
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2019-03-30 11:26:11 +02:00 |
Rejeesh Kutty
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15c3c96512
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ad9361- clkdiv to util_ad9361_divclk
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2017-08-07 11:25:55 -04:00 |
|
Istvan Csomortani
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c9eaa43b1e
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fmcomms5: Update UP instantiations
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2017-04-21 15:10:44 +03:00 |
|
Rejeesh Kutty
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9b6dd27c23
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ad9361- delay initialization
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2017-03-15 12:06:59 -04:00 |
|
Rejeesh Kutty
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c39ed08edd
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zcu102/*- actual clock == desired clock
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2017-02-06 12:53:47 -05:00 |
Adrian Costina
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9344dd34dc
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zcu102: Update project to include clkdiv
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2017-01-16 14:47:31 +02:00 |
Nick Pillitteri
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b622b6592e
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FMCOMMS5/ZCU102 : Merge from njpillitteri/hdl:dev
Pull request Dev #26
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2017-01-13 14:47:16 +02:00 |