1fff1076b1
daq2/a10gx- ethernet fix
2015-09-02 14:31:15 -04:00
01c0fdc809
daq2/a10gx- ethernet fix
2015-09-02 14:31:15 -04:00
1ecd615f92
common/mitx045 : Fix the vdma interface of axi_hdmi_core
2015-09-02 16:33:30 +03:00
9fb336e464
usdrx1: Add DDR FIFO
...
The converters on the usdrx1 generate 2.5GB/s. This more than we can
transport over the HP interconnects to the system memory.
Add a dedicated DDR FIFO to design which can be used to buffer the data
before it is transferred to the main memory.
Also increase the interconnect clock rate from 100MHz to 200MHz and the DMA
FIFO size from 4 to 8, so we can transfer the captured data faster to the
main memory.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
bbada6ed8f
usdrx1: Add overflow flag to ILA
...
It's useful to know if and when a overflow happens.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
c67aecc1eb
usdrx1: Disable SYNC_TRANSFER_START for the DMA
...
There is no sync signal in this design, so the flag needs to be set to 0.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
9b37d6bfe7
pzslb- updates - wip
2015-08-31 15:41:29 -04:00
49430dc2b0
pzslb- copy
2015-08-31 15:41:27 -04:00
879a75a690
pzslb- copy
2015-08-31 15:41:26 -04:00
fdc3dbb805
pzslb- copy
2015-08-31 15:41:25 -04:00
fc79af6edc
pzslb- common
2015-08-31 15:41:24 -04:00
f005de9ee2
pzslb- added
2015-08-31 15:41:23 -04:00
a67ae238f8
rfsom-ps7- ddr settings
2015-08-31 15:39:45 -04:00
212235189f
hdmi-tx- signal name changes
2015-08-28 13:48:33 -04:00
0e20277bc1
hdmi-tx- signal name changes
2015-08-28 13:48:33 -04:00
93fe70790d
hdmi-tx- signal name changes
2015-08-28 13:48:33 -04:00
810fced1ec
hdmi-tx- signal name changes
2015-08-28 13:48:33 -04:00
01852a14de
hdmi-tx- signal name changes
2015-08-28 13:48:33 -04:00
7a1df720e2
rfsom- tdd ensm io changes
2015-08-27 16:26:18 -04:00
6e90ba24e4
rfsom- add rgmii iodelay constraints
2015-08-27 16:26:17 -04:00
15be942b74
daq2-a10gx- ignore cpu2ddr-io paths
2015-08-27 13:54:05 -04:00
a92e049e8f
fmcomms2_bd- another attempt at ila width
2015-08-27 13:17:08 -04:00
90e4cadf4b
daq2/kcu105- xcvr pin loc
2015-08-27 12:40:44 -04:00
b8f9b7040d
fmcomms2- tdd ila fixes
2015-08-27 11:55:41 -04:00
026fad8853
fmcomm2- enable/txnrx- through devif
2015-08-27 11:41:58 -04:00
6a9790484f
fmcomm2- enable/txnrx- through devif
2015-08-27 11:41:56 -04:00
3953ab5e22
rfsom- rgmii upgrade
2015-08-27 11:41:55 -04:00
7c8e56cb09
daq2/kcu105- pin loc is now all errors
2015-08-27 11:18:00 -04:00
89c7a4de79
daq2/kcu105- parameter changes
2015-08-27 11:18:00 -04:00
58fa29b673
daq2- jesd core upgrade
2015-08-27 11:18:00 -04:00
2e1e0939ce
fmcomms2- dma parameters & ila cores upgrade
2015-08-26 14:12:57 -04:00
74a6e33f2d
kcu105: 2015.2.1 updates
2015-08-25 09:12:36 -04:00
4eb28592c8
kcu105: 2015.2.1 updates
2015-08-25 09:12:32 -04:00
971e3395e7
projects/scripts: Update board part names.
...
Property 'board' is deprecated for object type 'project', 'board_part' is used. Update the 'board_part' property names for all Xilinx development boards.
2015-08-25 10:19:57 +03:00
77e2eb7364
projects/common: Fix parameter name for xilinx core axi_gpio
...
Parameter C_GPDATA_WIDTH is changed to C_GPIO_WIDTH.
2015-08-25 10:07:11 +03:00
d3e090da3d
projects/common: Upgrade Xilinx's IP cores
...
To update the projects to Vivado 2015.2 the following IP cores were upgraded:
+ microblaze 9.4 to microblaze 9.5
+ axi_ethernet 6.2 to 7.0
+ mig 6.1 to 7.0
2015-08-25 10:03:49 +03:00
203d7cb470
projects/common: Cosmetic changes.
2015-08-25 09:58:32 +03:00
f08305c979
adv7511_ac701: Fix axi_ethernet core's port connections
2015-08-25 09:54:19 +03:00
af8a48d90e
projects: Fix broken parameters at the common block designs.
...
Fix parameter names for axi_spdif_tx and axi_i2s_adi core instantiations.
2015-08-25 09:25:24 +03:00
78cf0fce0e
ddr/eth- pll refclock is defined by the cores
2015-08-21 14:42:15 -04:00
827fc1e29a
remove auto-pack disable
2015-08-20 13:54:16 -04:00
9e5e7d6805
remove rfsom from fmcomms2
2015-08-20 10:33:43 -04:00
168bcecc31
pzsdr- added
2015-08-20 10:32:48 -04:00
2dabf98089
parameter changes
2015-08-20 08:54:13 -04:00
0dfb3e2019
tcl_scripts: Update Vivado version number to 2015.2.1
2015-08-20 10:50:52 +03:00
d52308f074
axi_dmac: Change parameter name 2D_TRANSFER
...
Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 10:14:22 +03:00
0ec17fd4d6
daq2-a10gx- parameter changes
2015-08-19 14:56:00 -04:00
0e587dd955
daq2/a10gx-- ad-rst unpack
2015-08-19 13:26:38 -04:00
fdeeef3d77
daq2/a10gx-- intmem to ddr
2015-08-19 13:26:38 -04:00
e760aa424a
daq2/a10gx-- intmem to ddr
2015-08-19 13:26:38 -04:00
Rejeesh Kutty
Istvan Csomortani
Lars-Peter Clausen