Istvan Csomortani
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7960b00684
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block_design: Update with new clock net variables
Using the new clock net variables in all Xilinx block designs.
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2019-06-11 18:13:06 +03:00 |
Laszlo Nagy
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b98eb28dca
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adrv9371: update adcfifo/dacfifo
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2019-01-23 14:45:45 +02:00 |
Michael Hennerich
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2e59a70cdd
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adrv9371: Increase FCLK2 to 200MHz to support max sampling rates
This fixes an issue seen when using 307.2 MSPS on the Observation RX.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
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2018-01-09 15:20:06 +01:00 |
AndreiGrozav
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a64998c3ff
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adrv9371x: Separate ps7 assignaments from common
Move the assignaments/connections for ps7 from common/adrv9371_bd
to zc706/system_bd
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2017-08-22 15:37:59 +03:00 |
Rejeesh Kutty
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fb4a583613
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projects/system_bd- adc/dac fifo board designs
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2017-02-27 16:06:39 -05:00 |
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Rejeesh Kutty
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edd5e9570f
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file renamed; sed output; fingers crossed
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2017-02-22 15:56:37 -05:00 |
|
Rejeesh Kutty
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ce1fed1ce6
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dmafifo- adc/dac split
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2016-08-16 12:54:39 -04:00 |
|
Istvan Csomortani
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3859cba186
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adrv9371x/zc706: Add PL_DDR FIFO to the design
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2016-05-27 14:13:55 +03:00 |
|
Rejeesh Kutty
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f92e8509bb
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adrv9371x- added
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2016-05-20 11:46:25 -04:00 |