For the AXI stream interface we want to generate TLAST only at the end of
the transfer, rather than at the end of each burst.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When all clocks are synchronous there are no synchronizers and the
constraint for the CDC registers can't find any cells which generates a
warning. To avoid this don't add CDC constraints when all the clocks are
synchronous.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The Qsys interconnect does not handle the assertion of BVALID on the
same cycle as [A]WREADY. Add a single cycle of delay to prevent
deadlocks.
Similar to:
2817ccdb22
("up_axi: altera can not handle same clock assertion of arready and rvalid")
Signed-off-by: Matthew Fornero <matt.fornero@mathworks.com>
Only enable bitstream compression only if both the
ADI_NO_BITSTREAM_COMPRESSION environment and TCL variable are not set.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Enabling bitstream compression reduces the size of the generated bitstream.
This means on one hand it will consume less storage, which is especially
useful for the BOOT partition of the ADI images where we store BOOT.BIN
files for all supported platforms.
On the other hand a smaller bitstream is faster to load from the storage
medium and it is also faster to program to the FPGA. So it reduces the
overall boot time as well.
The only downside of bitstream compression is that the bitstream size is no
longer constant, but depends on the actual design and resource utilization.
This will not work with bootloaders that expect a fixed size.
When building a bitstream using the tcl scripts bitstream compression can
be disabled by setting the ADI_NO_BITSTREAM_COMPRESSION environment
variable.
Initial tests show a reduction of a round 50% in size for most ADI
projects.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Rejeesh Kutty
Costina
Lars-Peter Clausen
Istvan Csomortani
István Csomortáni
Matthew Fornero
AndreiGrozav