Rejeesh Kutty
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aa6c94c993
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usdrx1/a5gt: ddr3 use ip constraints
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2016-12-22 14:14:21 -05:00 |
Istvan Csomortani
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f47863bbcf
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usdrx1: Integrate ad_syref_gen into the project
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2016-12-19 14:36:01 +00:00 |
|
Rejeesh Kutty
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f799c40cf0
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usdrx1/a5gt- xcvr interface changes
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2016-12-08 16:05:23 -05:00 |
Adrian Costina
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c200fc8019
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usdrx1: Updated a5gt project to Quartus 15
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2015-08-12 10:20:58 +03:00 |
|
Rejeesh Kutty
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4927ca85c2
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projects- jesd-align port name change
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2015-05-20 14:24:26 -04:00 |
|
Adrian Costina
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573acc8af6
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usdrx1: A5GT project updated to 14.1
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2015-05-08 15:04:44 +03:00 |
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Adrian Costina
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56374cf592
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usdrx1: Added synchronization, updated constraints, added timing check for a5gt project
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2014-10-29 19:29:42 +02:00 |
|
Adrian Costina
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8934a66013
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usdrx1: Update project so that the AD9671 cores can be synchronized
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2014-10-13 17:06:40 +03:00 |
|
Rejeesh Kutty
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adf4893a27
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usdrx1: remove constraints and other changes
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2014-10-09 15:25:08 -04:00 |
|
Adrian Costina
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2dfcb0c599
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usdrx1: Initial commit for a5gt
axi_ad9671: added start of frame information to the altera core.
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2014-10-07 19:41:54 +03:00 |