Istvan Csomortani
f003b5b35a
fmcjesdadc1: Reduce SYSREF period
2017-01-12 16:10:45 +02:00
Rejeesh Kutty
37d54bb984
fmcjesdadc1/a5gt- max delay fit only
2017-01-04 16:04:19 -05:00
Rejeesh Kutty
8b74e911b8
fmcjesdadc1/a5gt- qr to ddio max delay
2017-01-04 14:10:44 -05:00
Rejeesh Kutty
18660c7ab4
fmcjesdadc1/a5gt: ddr3 use ip constraints
2016-12-22 14:14:21 -05:00
Rejeesh Kutty
2bea337aa2
fmcjesdadc1/a5gt- use 50m-mem-cpu-clk
2016-12-22 14:14:21 -05:00
Rejeesh Kutty
5d683943ab
fmcjesdadc1/a5gt- remove ad-sysref-gen-pack
2016-12-22 14:14:21 -05:00
Rejeesh Kutty
4a783d523d
projects/altera* - default & common qsys commands
2016-12-20 16:27:44 -05:00
Istvan Csomortani
da7f4608a8
fmcjesdadc1/usdrx1: Clean up the mess
...
Delete accidentally commited generated files.
2016-12-19 15:35:20 +00:00
Istvan Csomortani
8d799d0316
fmcjesdadc1: Intergrate ad_sysref_gen into project
2016-12-19 13:37:29 +00:00
Adrian Costina
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
Rejeesh Kutty
85eac8c811
fmcjesdadc1/a5*- updates
2016-11-10 16:57:06 -05:00
Rejeesh Kutty
7a2c713a4e
fmcjesdadc1/a5* - hdlmake.pl
2016-11-10 11:37:06 -05:00
Rejeesh Kutty
c6730ab2d7
fmcjesdadc1/a5gt- updates
2016-11-10 11:36:41 -05:00
Rejeesh Kutty
c207589f4b
fmcjesdadc1/a5gt - qsys2tcl flow
2016-11-10 11:32:29 -05:00
Rejeesh Kutty
acb9bf3902
hdlmake- a5soc/a5gt- updates
2016-11-04 15:02:57 -04:00
Rejeesh Kutty
905e29eb01
hdlmake- altera
2016-10-10 12:55:55 -04:00
Istvan Csomortani
16ee1336c3
Makefile: Update make files
2016-09-15 11:41:06 +03:00
Adrian Costina
0b0aa8e6c0
Makefile: Add MMU option to altera makefiles
2016-08-11 17:46:54 +03:00
Istvan Csomortani
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
Istvan Csomortani
f784557895
lib_refactoring: IOBUF is a Xilinx macro, no need to use with Altera
2016-08-08 15:06:34 +03:00
Adrian Costina
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
Rejeesh Kutty
eaf4d4a19d
makefile updates
2016-06-10 14:26:14 -04:00
Adrian Costina
0f37dd6424
fmcjesdadc1: Fixed project
...
- changed system_project.tcl so that all base designs to be included
- changed DMA properties to take into consideration the new parameter names
- changed reset bridges to asynchronous
- increased maximum burst size of the DMA bridge
- changed the data_width of the memory bus to 256, as with 512 timing violations may occur
- changed base addresses for the base system to be the same as in the previous release
2016-02-19 14:09:57 +02:00
Adrian Costina
2309c4d83c
Makefiles: Removed " from path
2015-11-27 14:02:46 +02:00
Adrian Costina
159f6c1216
Makefiles: Updated Makefiles
...
- for altera projects, taken into consideration of the new location for common qsys files
- for fmcomms5, added wfifo dependency
- for daq3, added mfifo dependency
2015-11-27 12:39:42 +02:00
Adrian Costina
fd3910a915
fmcjesdadc1: Updated a5gt design
2015-11-24 15:39:21 +02:00
Adrian Costina
9d2b8809df
Makefiles: Updated Makefiles
2015-10-23 10:44:27 +03:00
Istvan Csomortani
a679251d7d
Makefiles: Update Make
2015-09-09 17:13:19 +03:00
Rejeesh Kutty
fb648ab6f5
moved to qsys
2015-07-23 15:26:21 -04:00
Rejeesh Kutty
3ccf1bef36
base system modifications
2015-07-23 15:23:10 -04:00
Adrian Costina
a7da779b94
Makefile: Updated Makefiles
2015-07-16 18:19:42 +03:00
Rejeesh Kutty
4e99a2cb01
xcvr: remove signal tap
2015-07-16 08:09:56 -04:00
Rejeesh Kutty
a454b73d27
fmcjesdadc1/a5gt: split xcvr cores
2015-07-15 09:44:53 -04:00
Rejeesh Kutty
226e23ca1f
fmcjesdadc1- xcvr components
2015-07-15 09:44:51 -04:00
Rejeesh Kutty
f64df40a0a
signal tap removed
2015-07-08 15:47:50 -04:00
Rejeesh Kutty
19bf05c740
signal tap removed
2015-07-08 15:47:48 -04:00
Rejeesh Kutty
bbf1c5b803
transceiver core added/gpio removed
2015-07-07 15:30:38 -04:00
Istvan Csomortani
46fa91d5be
Makefile: Update Make files
2015-07-03 18:08:57 +03:00
Rejeesh Kutty
18e8914087
fmcjesdadc1/a5gt: pn-errors version
2015-07-01 13:43:12 -04:00
Rejeesh Kutty
35aca98b5f
fmcjesdadc1/stap: added
2015-07-01 13:43:10 -04:00
Rejeesh Kutty
330c205e8e
fmcjesdadc1- sys_clk changes
2015-06-30 10:47:21 -04:00
Lars-Peter Clausen
6862655b0d
Add .gitattributes file
...
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Rejeesh Kutty
543e08b67a
fmcadc1: sdc updates
2015-06-25 04:25:39 -04:00
Rejeesh Kutty
15740a7d34
fmcjesdadc1- 15.0 updates
2015-06-24 05:31:09 -04:00
Rejeesh Kutty
f81d22a17a
altera- common timing check
2015-06-04 10:56:32 -04:00
Adrian Costina
c19749361d
Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
...
Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
Adrian Costina
1c9b41db6f
fmcjesdadc1: A5GT project, added modular sgdma for Ethernet, nios configured for linux
2015-05-08 14:51:24 +03:00
Adrian Costina
dc2b37bd0c
Makefile: Added top level Makefile. Modified behavior of clean and clean-all
...
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.
The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
Adrian Costina
374f82e7de
makefiles: The clean command for library won't remove the xml files, except for component.xml.
...
Updated also the dmac dependencies
2015-04-16 11:53:27 +03:00
Adrian Costina
780455d68c
Makefile: Updated makefiles. Added makefiles for altera
2015-04-09 17:57:06 +03:00