d3e090da3d
projects/common: Upgrade Xilinx's IP cores
...
To update the projects to Vivado 2015.2 the following IP cores were upgraded:
+ microblaze 9.4 to microblaze 9.5
+ axi_ethernet 6.2 to 7.0
+ mig 6.1 to 7.0
2015-08-25 10:03:49 +03:00
203d7cb470
projects/common: Cosmetic changes.
2015-08-25 09:58:32 +03:00
f08305c979
adv7511_ac701: Fix axi_ethernet core's port connections
2015-08-25 09:54:19 +03:00
af8a48d90e
projects: Fix broken parameters at the common block designs.
...
Fix parameter names for axi_spdif_tx and axi_i2s_adi core instantiations.
2015-08-25 09:25:24 +03:00
78cf0fce0e
ddr/eth- pll refclock is defined by the cores
2015-08-21 14:42:15 -04:00
827fc1e29a
remove auto-pack disable
2015-08-20 13:54:16 -04:00
9e5e7d6805
remove rfsom from fmcomms2
2015-08-20 10:33:43 -04:00
168bcecc31
pzsdr- added
2015-08-20 10:32:48 -04:00
2dabf98089
parameter changes
2015-08-20 08:54:13 -04:00
0dfb3e2019
tcl_scripts: Update Vivado version number to 2015.2.1
2015-08-20 10:50:52 +03:00
d52308f074
axi_dmac: Change parameter name 2D_TRANSFER
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Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 10:14:22 +03:00
0ec17fd4d6
daq2-a10gx- parameter changes
2015-08-19 14:56:00 -04:00
0e587dd955
daq2/a10gx-- ad-rst unpack
2015-08-19 13:26:38 -04:00
fdeeef3d77
daq2/a10gx-- intmem to ddr
2015-08-19 13:26:38 -04:00
e760aa424a
daq2/a10gx-- intmem to ddr
2015-08-19 13:26:38 -04:00
413c322145
base/daq2- updates
2015-08-19 13:26:38 -04:00
f40abf171f
cpack- adc_rst added
2015-08-19 13:26:38 -04:00
8cc3aa0865
ddr- 933/233
2015-08-19 13:26:38 -04:00
57cfb7cfb1
hdl/library: Update the IP parameters
...
The following IP parameters were renamed:
PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
10d9de39a1
axi_ad9361/tdd: Update the synchronization logic
...
The master will regenerate a sync pulse periodically. The period can be defined by software.
2015-08-19 12:21:23 +03:00
bcee3e04d4
fmcomms2_tdd: Update tdd_enabaled path
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This line controls the mux, which switch between hdl and software (GPIO) control of the ENABLE/TXNRX pins.
Fix the broken path and change the name from "tdd_enable" to "tdd_enabled".
2015-08-19 12:14:05 +03:00
f5de5ca487
usdrx1: Fixed jesd core parameters. Fixed synchronization mechanism
2015-08-19 10:12:24 +03:00
e221c3b48c
daq2- gt changes
2015-08-17 14:11:58 -04:00
c72cf99562
daq2- gt changes
2015-08-17 14:11:58 -04:00
b84afcdcd1
Merge branch 'master' into dev
...
Conflicts:
library/Makefile
library/axi_ad6676/axi_ad6676_ip.tcl
library/axi_ad9122/axi_ad9122_core.v
library/axi_ad9122/axi_ad9122_ip.tcl
library/axi_ad9144/axi_ad9144_ip.tcl
library/axi_ad9152/axi_ad9152_ip.tcl
library/axi_ad9234/axi_ad9234_ip.tcl
library/axi_ad9250/axi_ad9250_hw.tcl
library/axi_ad9250/axi_ad9250_ip.tcl
library/axi_ad9361/axi_ad9361.v
library/axi_ad9361/axi_ad9361_dev_if_alt.v
library/axi_ad9361/axi_ad9361_ip.tcl
library/axi_ad9361/axi_ad9361_rx_channel.v
library/axi_ad9361/axi_ad9361_tdd.v
library/axi_ad9361/axi_ad9361_tx_channel.v
library/axi_ad9625/axi_ad9625_ip.tcl
library/axi_ad9643/axi_ad9643_channel.v
library/axi_ad9643/axi_ad9643_ip.tcl
library/axi_ad9652/axi_ad9652_channel.v
library/axi_ad9652/axi_ad9652_ip.tcl
library/axi_ad9671/axi_ad9671_constr.xdc
library/axi_ad9671/axi_ad9671_ip.tcl
library/axi_ad9680/axi_ad9680_ip.tcl
library/axi_ad9739a/axi_ad9739a_ip.tcl
library/axi_dmac/axi_dmac_constr.sdc
library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl
library/axi_jesd_gt/axi_jesd_gt_constr.xdc
library/axi_jesd_gt/axi_jesd_gt_ip.tcl
library/axi_mc_speed/axi_mc_speed_constr.xdc
library/common/ad_gt_channel_1.v
library/common/ad_gt_common_1.v
library/common/ad_gt_es.v
library/common/ad_iqcor.v
library/common/ad_jesd_align.v
library/common/ad_rst.v
library/common/altera/ad_xcvr_rx_rst.v
library/common/up_adc_common.v
library/common/up_axis_dma_rx.v
library/common/up_axis_dma_tx.v
library/common/up_clkgen.v
library/common/up_clock_mon.v
library/common/up_dac_common.v
library/common/up_gt.v
library/common/up_hdmi_tx.v
library/common/up_tdd_cntrl.v
library/common/up_xfer_cntrl.v
library/common/up_xfer_status.v
library/util_cpack/util_cpack.v
library/util_cpack/util_cpack_ip.tcl
library/util_dac_unpack/util_dac_unpack_hw.tcl
library/util_jesd_align/util_jesd_align.v
library/util_jesd_xmit/util_jesd_xmit.v
library/util_upack/util_upack_ip.tcl
library/util_wfifo/util_wfifo.v
library/util_wfifo/util_wfifo_constr.xdc
library/util_wfifo/util_wfifo_ip.tcl
projects/arradio/c5soc/system_bd.qsys
projects/common/vc707/vc707_system_bd.tcl
projects/common/zc706/zc706_system_plddr3.tcl
projects/daq2/a10gx/Makefile
projects/daq2/a10gx/system_bd.qsys
projects/daq3/common/daq3_bd.tcl
projects/daq3/zc706/system_bd.tcl
projects/fmcjesdadc1/a5gt/Makefile
projects/fmcjesdadc1/a5gt/system_bd.qsys
projects/fmcjesdadc1/a5gt/system_constr.sdc
projects/fmcjesdadc1/a5gt/system_top.v
projects/fmcjesdadc1/a5soc/system_bd.qsys
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
projects/fmcomms1/ac701/system_bd.tcl
projects/fmcomms1/common/fmcomms1_bd.tcl
projects/fmcomms1/kc705/system_bd.tcl
projects/fmcomms1/vc707/system_bd.tcl
projects/fmcomms1/zc702/system_bd.tcl
projects/fmcomms1/zc702/system_top.v
projects/fmcomms1/zc706/system_bd.tcl
projects/fmcomms1/zc706/system_top.v
projects/fmcomms1/zed/system_bd.tcl
projects/fmcomms1/zed/system_top.v
projects/fmcomms2/ac701/system_constr.xdc
projects/fmcomms2/common/fmcomms2_bd.tcl
projects/fmcomms2/kc705/system_constr.xdc
projects/fmcomms2/kc705/system_top.v
projects/fmcomms2/mitx045/system_top.v
projects/fmcomms2/rfsom/system_constr.xdc
projects/fmcomms2/rfsom/system_top.v
projects/fmcomms2/vc707/system_top.v
projects/fmcomms2/zc706/system_bd.tcl
projects/fmcomms2/zc706/system_constr.xdc
projects/fmcomms2/zc706/system_top.v
projects/fmcomms2/zed/system_top.v
projects/imageon/zc706/system_constr.xdc
projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
projects/motcon2_fmc/zed/system_constr.xdc
projects/motcon2_fmc/zed/system_top.v
projects/usdrx1/a5gt/Makefile
projects/usdrx1/a5gt/system_bd.qsys
projects/usdrx1/common/usdrx1_bd.tcl
Conflicts were resolved using 'Mine' (/dev).
2015-08-17 15:15:58 +03:00
17b2a9f121
Merge branch 'master'
...
Merge master into release to sync the index files. The two changes are just mode changes. There aren't any functional changes in this commit!
2015-08-17 10:09:07 +03:00
f08633c0d5
fmcomms2: Add GPIO to the c5soc project
2015-08-13 18:14:39 +03:00
c200fc8019
usdrx1: Updated a5gt project to Quartus 15
2015-08-12 10:20:58 +03:00
489b31e929
ad9434_fmc: DMAC's destination clock must be more than or equal to adc_clk/4 (125 Mhz)
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DMAC's destination clock set to 200Mhz
2015-08-10 18:00:24 +03:00
10a3ce96fe
ad9434_fmc: DMAC's destination clock must be more than or equal to adc_clk/4 (125 Mhz)
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DMAC's destination clock set to 200Mhz
2015-08-10 17:57:52 +03:00
afb9911b6e
Makefiles: Updated makefiles
2015-08-06 19:50:50 +03:00
d2c99acae8
fmcomms2/TDD: Update synchronization interface
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Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 15:14:36 +03:00
cfc4046821
fmcomms2: Add a synchronization interface for TDD mode.
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Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-29 14:10:56 +03:00
8e631e56d6
fmcomms2: Add a synchronization interface for TDD mode.
...
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 14:42:54 +03:00
36f71ea59b
fmcjesdadc1: common altera, fixed dmac configuration and connection. Connected reset for cpack
2015-07-28 12:33:24 +03:00
0422c87846
a5soc/base- remove hdmi, led/switchs to gpio
2015-07-27 12:08:33 -04:00
2ca2bf9383
a5soc- all hps clocks
2015-07-27 12:08:33 -04:00
e488ba0287
a5soc- remove hdmi core
2015-07-27 12:08:32 -04:00
0c5958091e
fmcjesdadc1/a5soc- base/fmc split
2015-07-27 12:08:32 -04:00
0a5dc938cd
fmcjesdadc1/a5soc- base/fmc split
2015-07-27 12:08:32 -04:00
f5f9ec38e8
a5soc- base/fmc split
2015-07-27 12:08:32 -04:00
58e0884ff9
a5soc- board qsys file
2015-07-27 12:08:32 -04:00
4d7ff0ed15
a5gte: Update ethernet connections
2015-07-27 16:05:26 +03:00
31ab81d627
a5gt: Updated ethernet clock constraints
2015-07-27 16:02:51 +03:00
797d679c72
fmcomms2: Updated c5soc project with the latest cores. Tested with Quartus 15.0
2015-07-24 16:43:33 +03:00
816238bb6c
fmcjesdadc:A5gt, decreased destination bus width for DMAs to 256. Increased DMA FIFO to 32
...
With lower buswidth, if all 4 channels are captured some samples are lost
With fifo size of 64, there are timing violations in the DMAC
With this configuration, 65536 samples could be captured from all 4 channels with no sample lost
Because of the DMAC destination bus is 256, the number of samples to be captured must be a multiple of 16, otherwise the system will freeze. This will be corrected in software
2015-07-24 15:31:19 +03:00
289e73660b
removed- xcvr is now part of qsys
2015-07-23 15:26:51 -04:00
fb648ab6f5
moved to qsys
2015-07-23 15:26:21 -04:00
3ccf1bef36
base system modifications
2015-07-23 15:23:10 -04:00
a1733238df
fmcjesdadc1- base/board split up
2015-07-23 15:21:53 -04:00
3ea60bca5d
fmcjesdadc1: a5gt, design working with quartus 15.0
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- added cpack to the design
- removed 166 MHz clock as it is not needed. DMA destination is 512 bits
- removed clock bridge between DMA and DDR
2015-07-23 18:11:53 +03:00
d8e2196c75
fmcjesdadc1- board qsys
2015-07-22 15:44:04 -04:00
d66387f482
fmcjesdadc1- board qsys
2015-07-22 15:23:39 -04:00
3e2712cf18
a5gt-base: initial updates
2015-07-22 15:22:22 -04:00
64070b6f27
a5gt- base system
2015-07-22 15:04:59 -04:00
b325c0fc01
fmcomms2_zc702: Add SPI and GPIO interface for FREQCVT
2015-07-22 10:22:07 +03:00
28aea82952
fmcomms2_zc702: Add SPI and GPIO interface for FREQCVT
2015-07-22 10:16:04 +03:00
b4eac232db
a10gx- move cores inside qsys
2015-07-21 11:06:45 -04:00
fcc298d837
a10gx- move cores inside qsys
2015-07-21 11:06:17 -04:00
b3102b5095
daq2/a10gx-- xcvr+base changes
2015-07-21 11:01:45 -04:00
445c4c835d
daq2-bd: xcvr components
2015-07-21 10:54:23 -04:00
08e46c5ff2
a10gx-base: data-master connections
2015-07-21 10:53:54 -04:00
97b8468819
daq2- constraints
2015-07-20 09:32:17 -04:00
1d6a77049d
daq2- base/board split
2015-07-20 09:31:57 -04:00
4b8d764852
daq2- base system modifications
2015-07-20 09:31:44 -04:00
da2e7acacb
daq2- separate base/board systems
2015-07-20 09:31:15 -04:00
2f53dc4412
daq2- board system only
2015-07-20 09:30:32 -04:00
a87b8fbf94
a10gx- base system only
2015-07-20 09:29:30 -04:00
80dc3bf92f
daq2/a10gx: remove signal tap
2015-07-16 14:59:01 -04:00
1de74c0267
fmcadc4: Changed the SPI CS address similar to previous version
2015-07-16 18:22:05 +03:00
c949482574
fmcadc4: Set explicit PCORE_ID for AD9680
2015-07-16 18:21:49 +03:00
a7da779b94
Makefile: Updated Makefiles
2015-07-16 18:19:42 +03:00
4e99a2cb01
xcvr: remove signal tap
2015-07-16 08:09:56 -04:00
7c142178dd
daq2/a10gx- axi_jesd_xcvr sysref name changes
2015-07-15 15:59:52 -04:00
ffd767deb2
daq2/a10gx- axi_jesd_xcvr sysref name changes
2015-07-15 15:59:51 -04:00
6c0ad6ede8
daq3: bsplit/ccat -- removed
2015-07-15 13:05:53 -04:00
a454b73d27
fmcjesdadc1/a5gt: split xcvr cores
2015-07-15 09:44:53 -04:00
2d8fa2024b
fmcjesdadc1/a5gt: split xcvr cores
2015-07-15 09:44:52 -04:00
226e23ca1f
fmcjesdadc1- xcvr components
2015-07-15 09:44:51 -04:00
3b3fe4e642
fmcomms2/FREQCVT : Update GPIOs
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Add gpio_muxout_[tx/rx] GPIO lines and update SPI interface I/Os for the FREQCVT board
2015-07-15 15:34:45 +03:00
1dcbf5e5a2
fmcomms2/zc706: Fix GPIO connections
...
Fix GPIO connections for the FREQCVT board.
2015-07-15 15:12:01 +03:00
1f7745610e
daq2- ddr updates
2015-07-14 12:46:52 -04:00
a38339a3ec
fmcomms2/rfsom: Add GPIO control for the RF card
2015-07-14 13:12:54 +03:00
ba2029a6e8
fmcomms2/rfsom: Delete trailing whitespaces from system_constr.xdc
2015-07-14 13:12:53 +03:00
a37932d881
fmcadc4: Changed the SPI CS address similar to previous version
2015-07-14 11:11:33 +03:00
a2e7fb9491
daq2/a10gx: qsys signal tap version
2015-07-13 10:07:18 -04:00
825fddd034
transceiver split up outside qsys
2015-07-10 11:45:07 -04:00
8c0d74aa90
transceiver split up outside qsys
2015-07-10 11:44:42 -04:00
e40aac9ab6
transceiver split up outside qsys
2015-07-10 11:44:22 -04:00
30ea87e60b
fmcadc4: Set explicit PCORE_ID for AD9680
2015-07-09 19:55:58 +03:00
897c31ebbf
imageon: moved spdif_rx to DMA3 to be compatible with both zc706 and zed
2015-07-09 10:58:54 +03:00
f1dd2435b4
signal tap removed
2015-07-08 15:47:31 -04:00
c9e73b023d
signal tap removed
2015-07-08 15:46:52 -04:00
f64df40a0a
signal tap removed
2015-07-08 15:47:50 -04:00
19bf05c740
signal tap removed
2015-07-08 15:47:48 -04:00
c972779217
motcon2_fmc: updated util_gmii_to_rgmii and motcon2_fmc project for improved performance of the ethernet
...
- removed the delay controller from the top file and added it inside the util_gmii_to_rgmii core
- removed delay related xdc constraints as they are not needed
2015-07-08 16:23:33 +03:00
bbf1c5b803
transceiver core added/gpio removed
2015-07-07 15:30:38 -04:00
075b1e5424
daq2/a10gx: added axi_jesd_xcvr control
2015-07-07 10:22:36 -04:00
46fa91d5be
Makefile: Update Make files
2015-07-03 18:08:57 +03:00
8c98399c37
imageon_ZC706: Add axi_spdif_rx core to the design
2015-07-03 17:48:29 +03:00
27b786e92f
imageon_loopback: Use BUFIO for the HDMI clock buffer
...
Since we are just doing a loopback all the logic is contained within the
IO bank. By using a BUFIO instead of a BUFG we avoid having to route the
clock signal from the IO bank to the middle of the FPGA and back to the IO
bank. This reduces the skew between clock and the data signals and makes
sure that the we can use the same design over a range of different
resolutions without having to calibrate the delay.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:07:17 +02:00
02b5ce82ad
imageon_loopback: Invert transmit clock
...
The ADV7511 samples on the rising edge. Update the data on the falling
edge, this gives us a larger margin and improved signal stability.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:07:17 +02:00
281cab091c
imageon_loopback: Create a clock for hdmi_rx_clock
...
Create a clock for the HDMI clock to make sure that the timing paths are
properly constraint.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:07:17 +02:00
5b2877b66f
imageon_loopback: Use BUFIO for the HDMI clock buffer
...
Since we are just doing a loopback all the logic is contained within the
IO bank. By using a BUFIO instead of a BUFG we avoid having to route the
clock signal from the IO bank to the middle of the FPGA and back to the IO
bank. This reduces the skew between clock and the data signals and makes
sure that the we can use the same design over a range of different
resolutions without having to calibrate the delay.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:06:03 +02:00
f5fc3a4d2f
imageon_loopback: Invert transmit clock
...
The ADV7511 samples on the rising edge. Update the data on the falling
edge, this gives us a larger margin and improved signal stability.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:06:03 +02:00
10cc007c57
imageon_loopback: Create a clock for hdmi_rx_clock
...
Create a clock for the HDMI clock to make sure that the timing paths are
properly constraint.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:06:03 +02:00
95500d4022
fmcomms2_rfsom: Fix GPIO connections
2015-07-03 13:03:19 +03:00
32ae7c771a
fmcomms2_ALL: Add/fix ENABLE/TXNRX control
...
Add ENABLE/TXNRX control for TDD, and preserve backward compatibility for pin control with GPIOs
2015-07-03 12:55:37 +03:00
5208ebedd5
Revert "fmcomms2_ALL: Preserve backward compatibility for ENABLE/TXNRX control"
...
This reverts commit 6b15704b70
2015-07-03 10:20:50 +03:00
88f936cc86
imageon: Put HDMI input/output FF into the IOB
...
This gives us predictable delays as well as very small skew between the induvidual data lines.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-02 18:36:51 +02:00
94d1792aba
Revert "imageon: Connect raw data to ILA"
...
This reverts commit 9e4fb2d048
2015-07-02 18:36:51 +02:00
eb3a0c179b
imageon: Put HDMI input/output FF into the IOB
...
This gives us predictable delays as well as very small skew between the induvidual data lines.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-02 18:33:32 +02:00
e269fe1dd0
Revert "imageon: Connect raw data to ILA"
...
This reverts commit 9e4fb2d048
2015-07-02 18:33:32 +02:00
18e8914087
fmcjesdadc1/a5gt: pn-errors version
2015-07-01 13:43:12 -04:00
35aca98b5f
fmcjesdadc1/stap: added
2015-07-01 13:43:10 -04:00
68cb6df366
imageon: Connect raw data to ILA
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Connect the raw HDMI data as generated by the ADV7604 to the ILA. For
debugging it is quite useful to be able to compare the data before and
after conversion pipeline.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
c8a095f79c
imageon: Increase ILA buffer size
...
2048 samples is not even enough for one 1080p line. Increase it to 4096.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
cb18b2c0fd
imageon: Fix HDMI RX DMA data ILA probe width
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The DMA data output of the HDMI RX core is 64-bit wide.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
c372064302
Add .gitattributes file
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Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
6b15704b70
fmcomms2_ALL: Preserve backward compatibility for ENABLE/TXNRX control
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By default the ENABLE/TXNRX pins are controlled by GPIOs, if the TDD module is enabled, the TDD FSM will take over the control of these two pins.
2015-07-01 15:26:46 +03:00
0102e3e02c
fmcomms2_ALL: Preserve backward compatibility for ENABLE/TXNRX control
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By default the ENABLE/TXNRX pins are controlled by GPIOs, if the TDD module is enabled, the TDD FSM will take over the control of these two pins.
2015-07-01 13:54:01 +03:00
9e4fb2d048
imageon: Connect raw data to ILA
...
Connect the raw HDMI data as generated by the ADV7604 to the ILA. For
debugging it is quite useful to be able to compare the data before and
after conversion pipeline.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:03:03 +02:00
e429cb3f5c
imageon: Increase ILA buffer size
...
2048 samples is not even enough for one 1080p line. Increase it to 4096.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:44 +02:00
bcd12c8ead
imageon: Fix HDMI RX DMA data ILA probe width
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The DMA data output of the HDMI RX core is 64-bit wide.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:44 +02:00
330c205e8e
fmcjesdadc1- sys_clk changes
2015-06-30 10:47:21 -04:00
6bc24e25eb
stap- need to be qsys
2015-06-29 13:26:32 -04:00
d25e02d7ee
stap- need to be qsys
2015-06-29 13:26:20 -04:00
499357a65a
motcon2_fmc: Updated project to include XADC
...
- connected reset pin, as vivado reports the reset pin erroneously
- configured XADC in simultaneous sampling mode from XAUX0 and XAUX8
- connected XADC interrupt
- because in the project constraints some base pin constraints are overwritten, the project constraints are processed late
- GPI pins were assigned instead of the XADC GIO0 and GIO1, which were assigned to the XADC for external mux mode
- removed commented code
2015-06-29 16:56:25 +03:00
f32039f154
imageon: Hdmi_iic_rstn is accessible through a GPIO.
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Connect hdmi_iic_rstn to GPIO[33]
2015-06-29 10:49:59 +03:00
aef6f6b20b
imageon: Hdmi_iic_rstn is accessible through a GPIO.
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Connect hdmi_iic_rstn to GPIO[33]
2015-06-29 10:48:57 +03:00
6862655b0d
Add .gitattributes file
...
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
fcc185d769
Makefile: Updated makefiles
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- removed up_drp_control, up_delay_control dependencies where not needed
- added axi_jesd_gt core in the library makefile
- fixed timing tcl dependency for altera projects
2015-06-25 14:59:34 +03:00
543e08b67a
fmcadc1: sdc updates
2015-06-25 04:25:39 -04:00
15740a7d34
fmcjesdadc1- 15.0 updates
2015-06-24 05:31:09 -04:00
714d415804
daq2/a10gx- signaltap changes
2015-06-19 14:33:04 -04:00
51e6a74a3d
daq2/a10gx- add xmit swap
2015-06-19 14:32:59 -04:00
d6b1260678
daq2/a10gx- signal tap + gpio
2015-06-19 14:32:58 -04:00
67df6b3ea8
a10gx- disable lab cell on dsp input register
2015-06-19 14:32:54 -04:00
db76fe3298
tquest- generate the timing report file
2015-06-19 14:32:53 -04:00
c3ea99d1f8
fmcadc2: Fixed zc706 spi connection
2015-06-19 13:31:59 +03:00
9fa705c488
fmcadc2: Fixed zc706 spi connection
2015-06-19 13:13:02 +03:00
301226c766
fmcjesdadc1: Fixed mdc_mdio connection for kc705
2015-06-18 11:06:47 +03:00
f01ba54c5f
fmcomms1: Fixed mdc_mdio connection for kc705
2015-06-18 11:06:33 +03:00
009d33f0a0
ad9467: Fixed mdc_mdio connection for kc705
2015-06-18 11:06:20 +03:00
41799c55dc
fmcjesdadc1: Fixed mdc_mdio connection for kc705
2015-06-18 11:04:29 +03:00
6de154d2c2
fmcomms1: Fixed mdc_mdio connection for kc705
2015-06-18 11:04:00 +03:00
988f4fac8f
ad9467: Fixed mdc_mdio connection for kc705
2015-06-18 11:03:11 +03:00
e6d9735e54
fmcomms1: Fixed zed top file, the DAC dma was not correctly connected
2015-06-17 14:43:34 +03:00
2e46bda916
motcon2_fmc: Update project to use the latest util_gmii_to_rgmii
2015-06-16 17:43:10 +03:00
8fc0e0e62d
fmcjesdadc1: Fixed vc707 ethernet connections
2015-06-16 16:27:09 +03:00
142f802f54
adv7511: Fixed vc707 ethernet connections
2015-06-16 16:26:58 +03:00
a2f380ab64
fmcjesdadc1: Fixed vc707 ethernet connections
2015-06-16 15:31:17 +03:00
98ae6d567f
adv7511: Fixed vc707 ethernet connections
2015-06-16 15:30:47 +03:00
4c80013faf
projects/daq2: gt lane split
2015-06-12 15:56:03 -04:00
e6525136a9
daq2/common: axi_ad9144_fifo needs a proper reset sequence
...
Connect the axi_ad9144_fifo/dma_rst signal to sys_cpu_reset
2015-06-12 14:03:46 +03:00
f587aa42d9
a10gx- tx sync
2015-06-10 14:32:25 -04:00
e3e4af5c51
daq2/zc706: open ports
2015-06-10 14:25:58 -04:00
97ab5e0ef7
fmcomms1: Update project to integrate the new util_wfifo
2015-06-10 15:16:17 +03:00
3d86f140e5
usdrx1: Removed ILA as the ports from axi_jesd_gt were removed
2015-06-10 10:56:55 +03:00
1fcdeac054
fmcjesdadc1/common: The new GT module does not have integrated monitor/debug ports
2015-06-09 11:50:55 +03:00
2330d1e27d
daq1/common: The new GT module does not have integrated monitor/debug ports
2015-06-09 11:50:27 +03:00
00b8c171b8
a10gx: pll locked to reset controller
2015-06-08 15:00:11 -04:00
be6d6f627a
ad9265: Removed ILA
2015-06-08 15:03:34 +03:00
25e56a4d03
arradio: renamed fmcomms2 c5soc to arradio
2015-06-08 11:35:21 +03:00
dc7064ab95
fmcomms2/vc707 - wfifo changes
2015-06-05 12:44:04 -04:00
25f1ad73f0
fmcomms2/freqcvt: Update SPI interface I/O
2015-06-05 18:16:14 +03:00
f1e75963a2
fmcomms2: wfifo+pack changes
2015-06-05 09:20:50 -04:00
47469ad375
ad9434/ad9467 : Connect reset signal for AXI streaming interface of the device dma
2015-06-04 18:09:48 +03:00
3b1ea7e528
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch
...
598ece4c8d
2015-06-04 18:09:47 +03:00
a8a71b4971
alt-tq: common file
2015-06-04 11:00:25 -04:00
f81d22a17a
altera- common timing check
2015-06-04 10:56:32 -04:00
d111692608
daq2/a10gx- ddr-ref @133
2015-06-04 10:53:16 -04:00
886c24f597
tq-alt: added
2015-06-04 10:53:14 -04:00
264dbfed35
common: rfsom: Add constraints for the eth1 rx clock
...
Add clock rate constraints for the eth1 rx clock, otherwise the tools
assume the RX paths are unconstrained and creates a bitstream which
violates hold times which causes bit errors on the RX path.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-03 17:21:43 +02:00
71b5004b25
projects- drp moved to up-clock domain
2015-06-01 14:57:59 -04:00
f9ffaf457d
projects/daq2- drp moved to up clock
2015-06-01 13:39:26 -04:00
4a701d3895
a10gx- no-ddr
2015-06-01 11:00:02 -04:00
aa24c442f5
a10gx- no-ddr
2015-06-01 11:00:01 -04:00
5250635162
cn0363: Fix ad_iobuf signal names
...
The signal names for the ad_iobuf were recently changed, adjust the cn0363
project accordingly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-27 13:25:19 +02:00
73d7bc111e
cn0363: Add missing Makefiles
...
Those were accidentally overlooked during the initial commit of the project.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-26 18:44:24 +02:00
77eff35d67
motcon2_fmc: Fixed constraint for renamed port
2015-05-23 19:02:48 +03:00
29ca9e4b8c
vc707: common, fixed address range for flash
2015-05-23 00:14:08 +03:00
8bd5fa5802
kc705: Common, fixed address range for the flash. Changed the start address so that it won't interfere with other cores
2015-05-23 00:10:06 +03:00
f91fbf1bc1
ad9434_zc706: Fix SPI interface
2015-05-22 12:31:48 +03:00
a6cae6b477
iobuf: do is a system verilog keyword
2015-05-21 14:06:17 -04:00
ad3198f623
a10gx: top level fixes
2015-05-21 14:06:15 -04:00
c9832d2f84
Remove ad7175_zed project
...
This project has been superseded by the cn0363 project and can be removed.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
c53f8c15ee
Add CN0363 project
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Add support for the CN0363 (colorimeter) board connected to the ZED board.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
6b9906b22b
Refresh Makefiles
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Re-generate the Makefiles after a small update to the generation script:
- Entries are sorted alphabetically
- Empty dependency lines are skipped
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 14:21:54 +02:00
ebbc0c6ed5
fmcomms5: zc706, removed debug related ila, as the pins were removed from the AD9361 IP
2015-05-21 14:19:22 +03:00
a047d3990a
fmcadc2_vc707: Fix interrupts
...
+ Remove some trailing whitespaces
+ Fix interrupt connections
2015-05-21 11:03:16 +03:00
19b094cab5
daq2/a10gx- added jesd align
2015-05-20 15:39:27 -04:00
f1c30ac225
daq2/a10gx- qsys updates
2015-05-20 14:24:49 -04:00
4927ca85c2
projects- jesd-align port name change
2015-05-20 14:24:26 -04:00
52b6077a46
a10gx- 15.0 updates
2015-05-19 15:12:23 -04:00
0805da3b6b
fmcomms2/rfsom- enable dac delay
2015-05-18 16:45:54 -04:00
3e51d29f75
enable/txnrx- tdd changes
2015-05-18 14:28:20 -04:00
c19749361d
Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
...
Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
672a5a4dfa
a10gx- updates
2015-05-14 14:35:43 -04:00
b311b9dac6
a10gx- updates
2015-05-14 14:35:42 -04:00
3226ca4374
fmcadc4- ad9680 version
2015-05-11 13:55:02 -04:00
c28ff2ff9a
fmcadc4- ad9680 version
2015-05-11 13:55:02 -04:00
16541335e6
fmcadc4- ad9680 version
2015-05-11 13:55:02 -04:00
2cd1d8a591
fmcadc4- ad9680 version
2015-05-11 13:55:02 -04:00
0a6efaccca
fmcadc4- ad9680 version
2015-05-11 13:55:02 -04:00
848dac70d5
a10gx: updates--
2015-05-11 11:56:27 -04:00
dc0eea5f0f
a10gx: updates--
2015-05-11 11:56:26 -04:00
bdc3f3d807
a10gx: updates--
2015-05-11 11:56:24 -04:00
75e055dab9
daq2/a10gx- initial commit
2015-05-11 11:56:23 -04:00
515dfd88d4
a10gx- added
2015-05-11 11:56:22 -04:00
14b721682d
motcon1_fmc: Removed
2015-05-11 18:02:52 +03:00
3d4e9eb36a
ac701: common, commit ethernet reset pin
2015-05-11 16:41:28 +03:00
15618c9edf
daq2 : Integrate the DACFIFO into the supported projects.
...
+ All pack/unpack logic is made by the cpack and upack modules.
+ The DAC FIFO is integrated between the TX DMA and cpack.
+ All the top files are updated, all the projects compiled successfully.
2015-05-11 12:20:50 +03:00
bad821ba1c
sys_dmafifo: Update the p_sys_dacfifo process
...
Update the ports and parameters at util_dacfifo instantiation.
2015-05-11 12:20:47 +03:00
d9a124b767
fmcomms2_zc706: TDD integration, initial commit.
2015-05-11 12:20:45 +03:00
00335a2af2
Makefile: Fix ZC706 Makefiles with propper address for the mig file
2015-05-11 10:25:07 +03:00
81a20b4abb
rfsom- apisys lb updates
2015-05-08 15:22:17 -04:00
d515ab1b61
adv7511: AC701, update project to work at full HD resolution
2015-05-08 18:53:47 +03:00
293ec6a319
fmcomms2: c5soc project updated to 14.1
2015-05-08 17:44:16 +03:00
91279253ef
Makefiles: Added mig project file as a dependency for Microblaze based projects. Also updated usdrx1 a5gt Makefile
2015-05-08 15:31:40 +03:00
573acc8af6
usdrx1: A5GT project updated to 14.1
2015-05-08 15:04:44 +03:00
1c9b41db6f
fmcjesdadc1: A5GT project, added modular sgdma for Ethernet, nios configured for linux
2015-05-08 14:51:24 +03:00
68570c1815
vc707: Common system mig, updated datawidth to 256 from 128
2015-05-08 10:51:27 +03:00
d7a0f1ffe3
projects/imageon_loopback: Add the option of setting hdmi_iic_rstn externally.
2015-05-07 15:17:16 +03:00
949abcdc8f
Makefile: Updated makefiles so that the project recipe does not depend on lib
2015-05-06 14:58:29 +03:00
4f75414a1a
fmcomms1: Removed constraints that are not needed
2015-05-05 23:39:08 +03:00
1fcaf8fb63
fmcomms1: Updated AC701 project to meet timing. Reduced FIFO size for AD9643 DMA to 8
2015-05-05 23:37:01 +03:00
90a5bb81b6
cftl_cip: Updated project to work with the new util_pmod_adc core
2015-05-05 23:34:52 +03:00
95805f21fa
adv7511: Fixed system_top for mitx045 board
2015-05-05 10:08:11 +03:00
3517b6941c
adv7511:kcu105, axi_hdmi_tx, axi_spdif_tx constraints modified so they apply to ultrascale
2015-05-05 10:06:26 +03:00
319f821fab
zc706pr - makefile
2015-05-04 13:41:03 -04:00
ab85e2ba36
zc706pr - 706 partial reconfiguration
2015-05-04 12:36:57 -04:00
e489090fbb
scripts- initialize prcfg list
2015-05-04 12:34:19 -04:00
2a8703763e
zc706pr - 706 partial reconfiguration
2015-05-04 12:33:28 -04:00
c3dd9258e7
zc706: project mode
2015-05-04 10:25:12 -04:00
62acd37fee
zc706: project mode
2015-05-04 10:25:07 -04:00
e7a0da9089
fmcomms2 : Verify the existence of the PR license
...
The fmcomms2 runs by default on PR mode, if the project script does not find a PR license, will implement just the default mode.
2015-05-04 15:12:38 +03:00
4bb26caa13
itx045: default install
2015-05-01 16:19:10 -04:00
ad551a0073
itx045: updates
2015-05-01 16:18:43 -04:00
aced144916
itx045: updates
2015-05-01 16:18:23 -04:00
ff443655ca
itx045: add ps7 settings
2015-05-01 16:17:59 -04:00
26fb85583b
adi_project- prefix directory for gitignore & make clean
2015-05-01 13:18:12 -04:00
00cafd4df0
fmcomms2/zc706: add partial reconfiguration
2015-05-01 12:23:18 -04:00
3641d8f714
fmcomms2/zc706: add partial reconfiguration
2015-05-01 12:23:11 -04:00
75a81d67d8
fmcomms2/zc706: add partial reconfiguration
2015-05-01 12:23:07 -04:00
0dc4c9cda9
adi_project: added partial reconfiguration
2015-05-01 12:21:59 -04:00
140c622c8b
prcfg: common files
2015-05-01 11:48:09 -04:00
a8d4c916c1
fmcomms2_bd: remove axi3 switch
2015-05-01 11:47:29 -04:00
3b58785368
daq1: Updated jesd reset connection. Fixed dmac async configuration. Updated zc706 constraints
2015-04-30 12:14:03 +03:00
e332fa01c8
ad6676evb, daq2, fmcadc2, fmcjesdadc1, usdrx1: Updated jesd reset connection
2015-04-30 12:11:46 +03:00
1df48a2e6e
Add hdmiio_int pin.
2015-04-29 18:50:28 +03:00
19ef85cec3
vc707: Changed mig project to use BANK_ROW_COLUMN, as it seems this mode gives best performance
2015-04-28 17:15:58 +03:00
288b9cccff
Makefile: Added makefiles for imageon_loopback project. Updated axi_ad9152, util_gmii_to_rgmii, util_wfifo to include constraints file
2015-04-28 15:22:37 +03:00
252aa135eb
ad9739a: Changed dma and interconnect clock to 200mhz. Removed div_clk constraint, as it is autodetected
2015-04-28 15:14:31 +03:00
3fdda617a4
fmcomms1: updated common, changed DMAC fifo size and wfifo reset signal source
...
- changed DMAC FIFO size to 16, as it should be large enough
- connected wfifo reset to adc_rst from axi_ad9643 core
2015-04-28 14:58:04 +03:00
37bfb2ef4b
ad9265: Updated common, wfifo is reset by the adc_rst signal from axi_ad9265 core
2015-04-28 14:53:12 +03:00
1eebfd3155
projects/imageon_loopback: Initial commit.
2015-04-28 10:32:28 +03:00
e51edfbadb
adv7511: KC705 mdio pin name fix
2015-04-27 11:21:36 +03:00
7e6f2bfa15
ad9265: Updated constraints file.
2015-04-27 11:20:42 +03:00
272148eee5
rfsom: sdio 50mhz
2015-04-23 15:30:50 -04:00
7611c2ae17
kcu105: ddr mig rbc to rcb
2015-04-23 15:30:48 -04:00
bb185296d7
fmcadc2_vc707: Increase the BRAM FIFO size to its maximum: it can store 1M samples.
...
The 2^18 dma address width with a 64 dma data width will result a FIFO, what will be implemented by 512 RAMB36 cells.
This is a the maximum BRAM FIFO depth in case of the VC707.
2015-04-23 18:00:00 +03:00
f232a36141
common: Place HDMI interface registers into the IOB
...
The paths from the HDMI interface registers to the IO pads are
unconstrained. This means the P&R can in theory put the register anywhere
which could lead to stability issues on the interface, depending on what
else is in the fabric. To get predictable delays for the register to IO pad
path place the register into the IOB section.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
bd6c76f4ab
fmcomms5: Set DMA AXI type to AXI3 on ZYNQ
...
The HP memory ports on ZYNQ are AXI3. The AXI-DMAC supports both native AXI3
and AXI4, by configuring it for AXI3 there is no need for a protocol
converter inside the interconnect, that connects the DMAC to the HP port.
In addition to that also set the data width for the DMAC on the HP port side
to 64 so there is no need for a memory width converter in the interconnect.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
4ed7c9aee9
fmcomms2_pr: zc706: Fix ddr and fixed_io signal names
...
The toplevel input/output signal names are lower case, but the signals
connected to the system_wrapper are upper case. Since verilog is case
sensitive this leaves the toplevel input/output signals unconnected. Fix
this by using lower case names everywhere.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
558f2e89af
imageon: zc706: Fix ddr and fixed_io signal names
...
The toplevel input/output signal names are lower case, but the signals
connected to the system_wrapper are upper case. Since verilog is case
sensitive this leaves the toplevel input/output signals unconnected. Fix
this by using lower case names everywhere.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
1bb5b6e55f
adv7511: zc706: Fix ddr and fixed_io signal names
...
The toplevel input/output signal names are lower case, but the signals
connected to the system_wrapper are upper case. Since verilog is case
sensitive this leaves the toplevel input/output signals unconnected. Fix
this by using lower case names everywhere.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
a61a195e3f
Makefiles: Updated makefiles to add the new constraints as dependecies
2015-04-23 11:16:39 +03:00
e25cfb9d9f
rfsom: ddr configuration
2015-04-22 13:45:11 -04:00
a100ecd308
util_dacfifo: Update BRAM DAC Fifo
...
The fifo will be placed between the DMAC and the Upack module, all the interfaces were updated.
2015-04-21 15:45:56 +03:00
3fd830b038
fmcomms2: Use AXI3 interface for the DMA on ZYNQ
...
On ZYNQ the HP interconnects have a AXI3 interface. The DMA controller
supports both AXI4 and AXI3. By switching to AXI3 there is no need to create
a protocol converter between the DMA and the HP port.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 19:51:37 +02:00
71d4f3a474
fmcomms2: Don't mark synchronous paths as asynchronous for the DMAs
...
The AXI master interface and the register map AXI slave interface use the
same clock. No need to mark the interfaces as asynchronous. This removes the
need for CDC logic on those paths.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 19:51:37 +02:00
dc2b37bd0c
Makefile: Added top level Makefile. Modified behavior of clean and clean-all
...
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.
The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
374f82e7de
makefiles: The clean command for library won't remove the xml files, except for component.xml.
...
Updated also the dmac dependencies
2015-04-16 11:53:27 +03:00
8b5d1a8693
fmcadc2: Connect the second CS line for the external SPI interface
2015-04-15 19:08:17 +03:00
780455d68c
Makefile: Updated makefiles. Added makefiles for altera
2015-04-09 17:57:06 +03:00
afea42f444
rfsom: Use interface connection for the I2S stream
...
Use a interface connection for the I2S stream instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:26 +02:00
90e132d203
mitx045: Use interface connection for the I2S stream
...
Use a interface connection for the I2S stream instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
7f26bfe436
zed: Use interface connection for the I2S stream
...
Use a interface connection for the I2S stream instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
06e37b0082
common: zed: Use interface to connect I2C core to the I2C mixer
...
Use a interface connection for the I2C connection instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
7da59a435f
common: rfsom: Use interface connection for the HDMI DMA stream
...
Use a interface connection for the HDMI DMA stream instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
1f2ecaf037
common: mitx045: Use interface connection for the HDMI DMA stream
...
Use a interface connection for the HDMI DMA stream instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
1d66cf63b6
common: zc706: Use interface connection for the HDMI DMA stream
...
Use a interface connection for the HDMI DMA stream instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
ab5c7bb57b
common: zc702: Use interface connection for the HDMI DMA stream
...
Use a interface connection for the HDMI DMA stream instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
70deb1eed1
common: zed: Use interface connection for the HDMI DMA stream
...
Use a interface connection for the HDMI DMA stream instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
38722e569b
common: zed: Fix audio DMA reset signals
...
Make sure to connect the I2S and SPDIF core DMA reset signals to the correct net.
Fixes audio support on the ZED board.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
5f8e9a74ea
makefile: updated
2015-04-07 16:32:01 -04:00
6d0a2bf64c
axi_adcfifo: added
2015-04-07 16:21:39 -04:00
4f7f109056
util_adcfifo: added
2015-04-07 16:08:38 -04:00
02dfa865b4
fmcadc5_vc707: Fix system top.
2015-04-06 12:15:49 +03:00
0a8823361f
fmcjesdadc1/a5gt: 14.1 updates
2015-04-03 14:54:57 -04:00
3aac5f9494
fmcjesdadc1/a5gt: 14.1 updates
2015-04-03 14:54:55 -04:00
5abf60345c
fmcomms7: dac lane mux
2015-04-03 13:42:27 -04:00
26a1f48724
fmcomms7: dac lane mux
2015-04-03 13:42:27 -04:00
0b00073ce5
rfsom: add ddr parameters
2015-04-03 13:42:27 -04:00
49b8d389f6
fmcjesdadc1: Kc705, fixed system top,SPI
2015-04-03 18:28:26 +03:00
5afcfa37a7
ad6676evb: changed the dma clock
2015-04-03 18:27:46 +03:00
f79a152958
Makefiles: updated all makefiles adding clean functionality
2015-04-03 11:57:54 +03:00
51b5e4ddc5
fmcomms5: Moved the clock generation for dma transfer inside system_bd of the platform
2015-04-02 22:29:17 +03:00
a8b2292370
ad9265: Changed the dma clock
2015-04-02 22:27:55 +03:00
f15ff45afc
imageon_zed: Initial commit plus fix ILAs
2015-04-02 18:53:45 +03:00
2937445cce
fmcomms2_pr: Update project to the new frame work.
2015-04-02 16:06:08 +03:00
9745462d88
fmcomms2: VC707 fixed top file
2015-04-02 15:31:40 +03:00
9dac22c814
fmcomms2: ZC702 fixed GPIOs in top file
2015-04-02 15:30:41 +03:00
243a9bc992
fmcomms1: AC701 update project to new framework
2015-04-02 15:30:02 +03:00
0162009099
cftl_cip: Update project to the new frame work.
2015-04-02 15:14:04 +03:00
8ed301a264
AC701: Common, removed system clock constraint
2015-04-02 11:51:20 +03:00
408dc6f018
ac701_base: Change data and instruction memory range to 8kbyte
2015-04-02 11:34:20 +03:00
dbbdeeaa0c
fmcomms1: Updated AC701 project to new framework
2015-04-02 11:22:16 +03:00
a4e9dd5fc4
fmcomms2: KC705 updated project
2015-04-02 11:21:13 +03:00
0184d2a4c7
makefile: added
2015-04-01 16:30:05 -04:00
a16ded55cf
makefile: added
2015-04-01 16:30:04 -04:00
ef32088c25
makefile: added
2015-04-01 16:30:03 -04:00
d7671ecf6d
makefile: added
2015-04-01 16:30:02 -04:00
a7d40aa0f2
makefile: added
2015-04-01 16:30:00 -04:00
e9a4a41823
makefile: added
2015-04-01 16:29:59 -04:00
9dba2d1e3b
makefile: added
2015-04-01 16:29:58 -04:00
c0b0abd8b7
makefile: added
2015-04-01 16:29:57 -04:00
36868c5433
makefile: added
2015-04-01 16:29:55 -04:00
fe8fb8f5ed
makefile: added
2015-04-01 16:29:54 -04:00
c63dead379
makefile: added
2015-04-01 16:29:53 -04:00
5165129c92
makefile: added
2015-04-01 16:29:52 -04:00
1697f297f8
makefile: added
2015-04-01 16:29:50 -04:00
59698474af
makefile: added
2015-04-01 16:29:49 -04:00
596d9db915
makefile: added
2015-04-01 16:29:48 -04:00
968836011f
makefile: added
2015-04-01 16:29:47 -04:00
c99630cb49
makefile: added
2015-04-01 16:29:45 -04:00
a9fe02419e
makefile: added
2015-04-01 16:29:44 -04:00
15ad9c287f
makefile: added
2015-04-01 16:29:43 -04:00
c46866e78c
makefile: added
2015-04-01 16:29:42 -04:00
c5a67ad1cd
makefile: added
2015-04-01 16:29:41 -04:00
74d3d458da
makefile: added
2015-04-01 16:29:39 -04:00
b1cc047d04
makefile: added
2015-04-01 16:29:38 -04:00
25a6a75a32
makefile: added
2015-04-01 16:29:37 -04:00
c5ccd44ffb
makefile: added
2015-04-01 16:29:36 -04:00
006a4fd209
makefile: added
2015-04-01 16:29:34 -04:00
61bdb437b1
makefile: added
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970d5f8c3e
makefile: added
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5f149535b5
makefile: added
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48e8945ac1
makefile: added
2015-04-01 16:29:29 -04:00
1c1464876c
makefile: added
2015-04-01 16:29:28 -04:00
56615a19f2
makefile: added
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1a14a36db6
makefile: added
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c085fbdd35
makefile: added
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077d2699fe
makefile: added
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d50bf705ef
makefile: added
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9e8cb22c96
makefile: added
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0a62cc9b8e
makefile: added
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661cdc5752
makefile: added
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0275f5575b
makefile: added
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b7d72a5b2e
makefile: added
2015-04-01 16:29:16 -04:00
71adb70844
makefile: added
2015-04-01 16:29:14 -04:00
1165203964
makefile: added
2015-04-01 16:29:13 -04:00
e596a1c593
makefile: added
2015-04-01 16:29:12 -04:00
6391b9aa9d
makefile: added
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565839db38
makefile: added
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14c36b172f
makefile: added
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ae960e66e9
makefile: added
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f3c151eb7c
makefile: added
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12e9ab7bdd
makefile: added
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4e3e26a8dd
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b6d5e21133
makefile: added
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0dc0d825a6
makefile: added
2015-04-01 16:29:01 -04:00
283427647b
makefile: added
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61293e7231
makefile: added
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73b31cfea0
makefile: added
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79a07e737d
makefile: added
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b3c666cf0d
makefile: added
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7a505f2d81
makefile: added
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8c25254fd7
makefile: added
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0664fb76f0
makefile: added
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3051afd7da
makefile: added
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d8ca123557
makefile: added
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88676c8c00
makefile: added
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786690cdae
makefile: added
2015-04-01 16:28:46 -04:00
861341df2d
makefile: added
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69e817aed7
makefile: added
2015-04-01 16:28:43 -04:00
8595341c32
makefile: added
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1c558f23db
makefile: added
2015-04-01 16:28:41 -04:00
d5562e6a63
makefile: added
2015-04-01 16:28:39 -04:00
47331d951a
makefile: added
2015-04-01 16:28:38 -04:00
2c8939f246
makefile: added
2015-04-01 16:28:37 -04:00
9ca85e9837
makefile: added
2015-04-01 16:28:36 -04:00
4a197f532e
makefile: added
2015-04-01 16:28:34 -04:00
26f176f2b5
makefile: added
2015-04-01 16:28:33 -04:00
f330a82bb5
makefile: added
2015-04-01 16:28:32 -04:00
544d4f579f
makefile: added
2015-04-01 16:28:30 -04:00
2fdc3d6d96
makefile: added
2015-04-01 16:28:29 -04:00
df7c64be5f
makefile: added
2015-04-01 16:28:28 -04:00
3520884406
makefile: added
2015-04-01 16:28:27 -04:00
aa1739cb3e
makefile: added
2015-04-01 16:28:25 -04:00
affa42d76a
makefile: added
2015-04-01 16:28:24 -04:00
c87268e703
makefile: added
2015-04-01 16:28:23 -04:00
4cf4349e27
makefile: added
2015-04-01 16:28:22 -04:00
98c2deaf26
imageon_zc706: Update project
...
+ Connect the Rx path to HP2
+ Enable AXI_SLICE_DEST
+ Add ILA to the dma_fifo and dma_axi_s2mm interface
+ Fix constraints
2015-04-01 18:50:18 +03:00
271a383012
ad9467_kc705: Update project to the new frame work.
2015-04-01 17:16:47 +03:00
1819a41ab5
ad9467_zed: Update project to the new framework.
2015-04-01 14:38:39 +03:00
fbfbfdaf87
motcon2_fmc: Updated to the latest framework
2015-04-01 11:45:01 +03:00
e58e9bc701
fmcomms5: Updated zc702 project to the latest framework
2015-03-31 17:44:09 +03:00
fb3ee53790
fmcomm5: Updated ZC706 project
2015-03-31 17:43:30 +03:00
92aa58826d
fmcomms5: Updated project to be compatible with both ZC702 and ZC706
2015-03-31 17:42:44 +03:00
207b9679c9
fmcomms2: miniITX project updated to the new framework
2015-03-31 16:17:58 +03:00
bf1a50ef0c
mitx: common, fixed number of gpios enabled
2015-03-31 16:16:40 +03:00
7d1c715f09
adv7511_vc707: Fix system top.
2015-03-31 11:00:48 +03:00
8f2fdec838
ad6676evb/vc707: 2014.4 updates
2015-03-30 14:59:09 -04:00
c4a7730c89
ad6676evb/vc707: 2014.4 updates
2015-03-30 14:59:09 -04:00
7f2cc2117c
ad6676evb/vc707: 2014.4 updates
2015-03-30 14:59:09 -04:00
edcc0672d2
ad6676evb/vc707: 2014.4 updates
2015-03-30 14:59:09 -04:00
7aeeaec5f4
fmcomms1: VC707 updated to the latest framework
2015-03-30 18:09:57 +03:00
89b83f8a00
fmcomms1: KC705 project updated to the latest framework
2015-03-30 18:09:17 +03:00
11379939d0
fmcjesdadc1: VC707, Updated project to the latest framework
2015-03-30 18:08:19 +03:00
c7e4ba5083
fmcjesdadc1: Updated KC705 to the latest flow
2015-03-30 18:07:47 +03:00
4f69ae19c5
adv7511_mitx045: Update latest frame work.
2015-03-30 17:54:37 +03:00
fcb163062f
adv7511 : Fix top for kcu105 and kc705
2015-03-30 16:21:38 +03:00
c00633d1ac
adv7511_ac701: Update project and common files to the new framework.
2015-03-30 15:23:26 +03:00
166c78060c
adv7511_vc707: Fix system top.
2015-03-29 16:17:08 +03:00
7e539632e5
adv7511_kc705: Fix system top.
2015-03-29 16:16:11 +03:00
e116822059
imageon_zc706: Updates and fixes
...
+ sync the sof to the dma_de signal
+ hdmi_rx_dma is connected to the HP1
+ fix syncronization signal in the CSC module
+ hdmi_rx_clk is asynchronous
2015-03-27 18:57:32 +02:00
e7c33bc7d8
ad9265_fmc: Fixed spi connection. Changed ila clock to 200 MHz
2015-03-27 15:40:28 +02:00
01f8c373b0
fmcomms1: Updated zc702 project to the latest framework
2015-03-27 15:38:46 +02:00
dbcf8389b3
fmcomms1: Updated zed project to the latest framework
2015-03-27 15:37:50 +02:00
8bc589a4d4
fmcadc2/vc707: 2014.4 updates
2015-03-26 15:07:17 -04:00
a24c1d33e9
fmcadc2/vc707: 2014.4 updates
2015-03-26 15:07:15 -04:00
86512ad95a
fmcadc2/vc707: 2014.4 updates
2015-03-26 15:07:10 -04:00
cf85f0b0bb
daq2/vc707: gpio_bd is 21bits
2015-03-26 14:18:26 -04:00
90a8d91c36
daq2/vc707: 2014.4 updates
2015-03-26 14:02:43 -04:00
17918bf735
daq2/vc707: 2014.4 updates
2015-03-26 14:02:39 -04:00
6b1eac4211
daq2/vc707: 2014.4 updates
2015-03-26 14:02:34 -04:00
6a85724793
daq2/vc707: 2014.4 updates
2015-03-26 14:02:31 -04:00
5014b4209c
kc705/vc707: consistency fixes
2015-03-26 14:02:10 -04:00
67c8d02110
kc705/vc707: consistency fixes
2015-03-26 14:00:58 -04:00
1fcccacdf5
kc705/vc707: consistency fixes
2015-03-26 14:00:50 -04:00
276bb9525a
daq2/kc705: 2014.4 updates
2015-03-26 10:14:12 -04:00
a7e3d2af67
daq2/kc705: 2014.4 updates
2015-03-26 10:14:12 -04:00
803ef90fea
daq2/kc705: 2014.4 updates
2015-03-26 10:14:12 -04:00
daac204676
kc705: gpio bd
2015-03-26 10:14:12 -04:00
ee2cd034bc
scripts: add gnd/vcc connections
2015-03-26 10:08:01 -04:00
f1e542abe3
adv7511_vc707: Constraint file added.
2015-03-26 13:03:51 +02:00
2d05193093
adv7511_zc702: Update project to the new framework.
2015-03-26 12:20:31 +02:00
d1e4727066
adv7511_vc707: Update project to the new framework.
2015-03-26 12:20:30 +02:00
feb29d57a5
adv7511_kcu105: PCORE_DEVICE_TYPE is a carrier specific parameter.
...
Move the PCORE_DEVICE_TYPE parameter from common to system_bd.
2015-03-26 12:20:28 +02:00
7c289c8844
adv7511_kc705: Update project to the new framework.
2015-03-26 12:20:27 +02:00
ccf0542218
fmcjesdadc1: Connected constant 0 to unconnected inputs
2015-03-26 12:08:14 +02:00
1828a94446
fmcomms5: Updated common and ZC706 project to the latest framework
2015-03-25 17:42:11 +02:00
10f3ac4d22
fmcomms1: Updated common and ZC706 project to the latest flow
2015-03-25 17:41:14 +02:00
037484e1d0
usdrx1: Updated project to the latest framework
2015-03-25 17:39:51 +02:00
754f11e0e6
imageon: updates
2015-03-24 15:08:48 -04:00
007a1ea3a4
imageon: updates
2015-03-24 15:08:48 -04:00
0085b8a712
imageon: updates
2015-03-24 15:08:48 -04:00
4bb8712e71
imageon: updates
2015-03-24 15:08:48 -04:00
b774379796
fmcomms2_zc706: Clean up system top
2015-03-24 13:38:48 +02:00
fcbbfa0177
fmcomms2_pr ZC706: Update project to the new framework
2015-03-24 13:37:37 +02:00
75d2c7e93e
daq1_zc706: Update project to the new framework
2015-03-24 12:45:24 +02:00
d418c9f9b1
fmcjesdadc1: Updated project to new flow. Updated ZC706 design
2015-03-24 10:38:14 +02:00
58a5e0142c
ad9265_fmc: Updated project to the new flow
2015-03-24 10:37:06 +02:00
919c02b57a
cftl_std: Update project to the new framework
2015-03-23 16:03:15 +02:00
d93b967980
fmcadc5: 2014.4 updates
2015-03-23 10:00:46 -04:00
624d2778d8
fmcadc5: 2014.4 updates
2015-03-23 10:00:46 -04:00
6dca97dd20
fmcadc5: 2014.4 updates
2015-03-23 10:00:46 -04:00
a09075030c
fmcadc5: 2014.4 updates
2015-03-23 10:00:46 -04:00
a74c61d6d5
vc707: gpio_bd changes
2015-03-23 10:00:46 -04:00
7c921474bf
adv7511_zed: Update project to the new framework
2015-03-23 13:01:51 +02:00
8443e94442
ad9434_fmc: Update project to the new framework
2015-03-23 13:00:50 +02:00
43673f6b9d
imageon_zc706: Update the project to the new framework
2015-03-23 12:45:34 +02:00
c1c6787b91
fmcomms2: Updated VC707 design with the latest base design
2015-03-20 18:22:48 +02:00
69326a72ef
VC707: Updated base design
2015-03-20 18:20:44 +02:00
b12187433d
adv7511_zc706: Interrupts and framework updates
2015-03-20 13:30:24 +02:00
cba3dde3dc
fmcadc4: 2014.4 updates
2015-03-19 16:33:14 -04:00
9e1e4969ff
fmcadc4: 2014.4 updates
2015-03-19 16:33:14 -04:00
9f727776e9
fmcadc4: 2014.4 updates
2015-03-19 16:33:14 -04:00
34d95c1969
fmcadc4: 2014.4 updates
2015-03-19 16:33:14 -04:00
1354836799
fmcadc4: 2014.4 updates
2015-03-19 16:33:14 -04:00
7e0bfca0c6
fmcadc4: 2014.4 updates
2015-03-19 16:33:14 -04:00
ee87421419
fmcomms6: 2014.4 updates
2015-03-19 15:36:52 -04:00
4d91d85265
fmcomms6: 2014.4 updates
2015-03-19 15:36:51 -04:00
5192adf5a7
fmcomms6: 2014.4 updates
2015-03-19 15:36:50 -04:00
c8d60d249b
fmcomms6: 2014.4 updates
2015-03-19 15:36:48 -04:00
9571ce3e3b
fmcomms6: 2014.4 updates
2015-03-19 15:36:47 -04:00
de14146b0b
fmcadc2: 2014.4 updates
2015-03-19 13:22:30 -04:00
771215cbbc
fmcadc2: 2014.4 updates
2015-03-19 13:22:30 -04:00
01de3e7984
fmcadc2: 2014.4 updates
2015-03-19 13:22:30 -04:00
b4bee697cb
fmcadc2: 2014.4 updates
2015-03-19 13:22:30 -04:00
126158629c
fmcadc2: 2014.4 updates
2015-03-19 13:22:30 -04:00
275ce42bc9
daq3: 2014.4 updates
2015-03-19 12:45:55 -04:00
caa0e27bd6
daq3: 2014.4 updates
2015-03-19 12:45:54 -04:00
423b436601
daq3: 2014.4 updates
2015-03-19 12:45:52 -04:00
0c94ea8d2b
daq3: 2014.4 updates
2015-03-19 12:45:51 -04:00
2fa475cca2
daq3: 2014.4 updates
2015-03-19 12:45:50 -04:00
ec0b6ac754
ad9739a/zc706: 2014.4 updates
2015-03-19 11:36:27 -04:00
c236c38e93
ad9739a/zc706: 2014.4 updates
2015-03-19 11:36:27 -04:00
18112d723f
ad9739a/zc706: 2014.4 updates
2015-03-19 11:36:27 -04:00
8542c2b0d7
rfsom: sd1 to sd0 changes
2015-03-19 09:34:15 -04:00
d72c525b46
rfsom: sd1 to sd0 changes
2015-03-19 09:34:14 -04:00
fb5966f9fd
rfsom: sd1 to sd0 changes
2015-03-19 09:34:13 -04:00
6cc8f142f1
rfsom: sd1 to sd0 changes
2015-03-19 09:34:12 -04:00
f0d08abe03
fmcomms2: Fix system_top.v for a few carrier
...
Interrupts are connected inside IPI. Fix system_top for zed, zc702, zc706 and kc705.
2015-03-18 10:37:24 +02:00
72b41c981f
kc705_base: Fix base address overlap
2015-03-18 10:33:17 +02:00
9b6531f79f
ad6676evb: 2014.4 updates
2015-03-17 16:53:13 -04:00
ee89862de9
ad6676evb: 2014.4 updates
2015-03-17 16:53:13 -04:00
1da8356f05
ad6676evb: 2014.4 updates
2015-03-17 16:53:13 -04:00
7456ca67a8
ad6676evb: 2014.4 updates
2015-03-17 16:53:13 -04:00
08a773b92d
fmcomms2/rfsom: interrupt fix
2015-03-17 16:31:12 -04:00
a92c5cb4ff
fmcomms7: 2014.4 updates
2015-03-17 14:01:47 -04:00
18891d036b
fmcomms7: 2014.4 updates
2015-03-17 14:01:47 -04:00
b2e05ce108
fmcomms7: 2014.4 updates
2015-03-17 14:01:47 -04:00
3e73b711e8
fmcomms7: 2014.4 updates
2015-03-17 14:01:47 -04:00
8cb96533d3
fmcomms7: 2014.4 updates
2015-03-17 14:01:46 -04:00
7bdce3837e
fmcomms2: Update interrupts
...
The new interrupts connections are made inside IPI by the process called 'ad_cpu_interrupt'.
2015-03-16 19:13:45 +02:00
65b16551c3
fmcomms2_kc705: Fix system_top connections
2015-03-16 19:12:04 +02:00
cea2d90eb2
base_kc705: Fix different issues
...
+ No more constant block inside IPI.
+ Gpio switch/led is on the axi_gpio first channel.
+ Fix the address map
+ Remove hdmi/spdif related constraints from base constraints
2015-03-16 19:10:57 +02:00
65654b77ff
fmcomms2_kc705: Update design to the new hdl framework
2015-03-13 18:54:28 +02:00
7befef6662
fmcomms2_zed: Update design to the new hdl framework
2015-03-13 18:52:57 +02:00
f7dd466469
adi_board.tcl : Fix some issue with the ad_mem_hpx_interconnect
...
Sometimes the find_bd_objs does not do its job, so need to double check that the interface clock is already connected to the p_clock or not.
Not sure about the cause of this behavior, need more investigation. Issue was found first at KC705 base design.
2015-03-13 18:51:21 +02:00
70e1d13a7b
fmcomms2: Updated project
2015-03-13 12:49:17 +02:00
ea303c6f61
zc702: Updated base design to the latest model
2015-03-13 12:44:08 +02:00
17d8c1b72b
daq2: move intrs into ipi
2015-03-12 16:17:17 -04:00
3a2d1004b5
daq2: move intrs into ipi
2015-03-12 16:17:09 -04:00
b1b46ed820
daq2: move intrs into ipi
2015-03-12 16:17:04 -04:00
ff3dcbc2cb
daq2: move intrs into ipi
2015-03-12 16:16:55 -04:00
8ad8ec4d1e
ml605 removed
2015-03-12 13:00:28 -04:00
e520f5c55a
ad9671_fmc: removed
2015-03-12 12:00:46 -04:00
73680d1ed9
fmcomms2/ml605: removed
2015-03-12 11:59:18 -04:00
18c03a57f8
adv7511/mb: added board files
2015-03-12 11:09:32 -04:00
7f462a1b34
adv7511/mb: added board files
2015-03-12 11:09:27 -04:00
15967f913f
adv7511/mb: added board files
2015-03-12 11:09:20 -04:00
8d0c3573cc
adv7511/kcu105: hdmi/spdif moved out of base design
2015-03-11 15:22:39 -04:00
491b67c13a
adv7511/kcu105: hdmi/spdif moved out of base design
2015-03-11 15:22:39 -04:00
68361bafd4
zc706_base: The FCLK_CLK2 is not used.
2015-03-11 18:10:32 +02:00
a3e73a1837
ad9467_fmc: Fix port names at ILA logic
...
In the version 2014.2 the output port of a constant module was changed from 'const' to 'dout'.
This commit fix the non working ILA.
2015-03-11 14:45:02 +02:00
543bfe9d44
daq2/kcu105: removed hdmi/spdif
2015-03-10 16:15:16 -04:00
ae16aeb064
kcu105/adv7511: moved hdmi/spdif out of base design
2015-03-10 16:15:15 -04:00
d7993401e6
kcu105/adv7511: moved hdmi/spdif out of base design
2015-03-10 16:15:14 -04:00
09b916d0c7
kcu105/adv7511: moved hdmi/spdif out of base design
2015-03-10 16:15:13 -04:00
20b2c19987
kcu105/adv7511: moved hdmi/spdif out of base design
2015-03-10 16:15:11 -04:00
ad41d250a8
kcu105/adv7511: moved hdmi/spdif out of base design
2015-03-10 16:15:10 -04:00
1cf8092ba9
fmcomms2/zc706: spi/gpio changes
2015-03-10 16:06:22 -04:00
631c71373a
fmcomms2/zc706: spi/gpio changes
2015-03-10 16:06:18 -04:00
796a0f4f2b
fmcomms2/zc706: spi/gpio changes
2015-03-10 16:06:13 -04:00
8967903d76
zc706: intr sensitivity level-high
2015-03-10 16:05:05 -04:00
7012172f66
fmcomms2: spi/gpio moved to base design
2015-03-10 15:27:32 -04:00
7da65ef3db
fmcomms2: spi/gpio moved to base design
2015-03-10 15:27:28 -04:00
abae36b12f
fmcomms2: spi/gpio moved to base design
2015-03-10 15:27:22 -04:00
9e57e919c4
fmcomms2: spi/gpio moved to base design
2015-03-10 15:26:57 -04:00
a68463d033
rfsom: board updates
2015-03-10 15:26:31 -04:00
e38356b243
rfsom: board updates
2015-03-10 15:26:24 -04:00
c0eef42647
adi_board: enable ps7 hp if needed
2015-03-09 16:12:23 -04:00
59457cb3d4
daq2/zc706: base system updates
2015-03-09 16:10:56 -04:00
ce5ece5494
daq2/zc706: base system updates
2015-03-09 16:09:54 -04:00
104782af87
daq2/kcu105: base system updates
2015-03-09 16:09:07 -04:00
548ae9d39e
daq2: move gpio/spi to base design
2015-03-09 16:08:25 -04:00
f0395b646c
plddr3: ad_connect updates
2015-03-09 16:07:37 -04:00
031dffa80c
zc706: move gpio/spi to base design
2015-03-09 16:07:02 -04:00
2302f282d3
sys_dmafifo: ad_connect updates
2015-03-09 16:06:06 -04:00
545c0baada
kcu105: gpio led/sw merged to bd default
2015-03-09 16:05:28 -04:00
b31d9abd91
kcu105: gpio/spi moved to base design
2015-03-09 16:04:09 -04:00
ed28b47203
board: optimize interconnect for performance
2015-03-06 12:38:52 -05:00
d5eaadd872
daq2: remove ila for kcu105 ddr-300M timing
2015-03-06 12:38:08 -05:00
1db5f4696f
kcu105: isolate ddr-300M from interconnect-100M timing
2015-03-06 12:37:31 -05:00
da5b136f5a
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
0ac1676318
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
7fba7cc6e5
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
af465cbc80
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
1220b53c8c
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
75c4228987
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
605d23d3a4
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
91765fdd82
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
7bf4141a3f
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
bf1388b05e
kcu105: rev.d changes
2015-03-04 12:43:04 -05:00
4f918cdce9
2014.4.1 ultrascale updates
2015-02-26 16:10:57 -05:00
847c2e049a
kcu105: removed lutram constraints
2015-02-26 16:09:55 -05:00
1613f7fb41
cftl_cip: Add util_pmod_fmeter IP to library
...
Frequency meter IP for CN0332.
2015-02-23 17:20:12 +02:00
abde4048e0
fmcomms1: Add extra AXI slice on ADC DMA path
...
Add a extra AXI slice on the ADC DMA data path to the HP interconnect to
improve the timing.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-20 16:43:45 +01:00
b9d16a7eb1
scripts: renaming board parameters
2015-02-20 09:12:30 -05:00
288f5378ff
rfsom: schematic changes
2015-02-18 14:32:41 -05:00
93e2bcd911
rfsom: schematic changes
2015-02-18 14:32:30 -05:00
383cf3b3a3
rfsom: schematic changes
2015-02-18 14:32:20 -05:00
d2e9b1fe03
rfsom: schematic changes
2015-02-18 14:32:04 -05:00
3113abf038
cftl_cip: Add gpio counter for CN0332
...
Add a counter core to the design, to support the CN0332 pmod with a speed sensor.
Change a naming for the custom cores.
2015-02-18 18:24:46 +02:00
e111e1336e
conflicts-
2015-02-06 22:14:21 -05:00
2d607d765b
cftl_cip: Add a clock input to the device core, for the SPI clock.
...
This clock can be adjustable from the system_project.tcl
2015-02-04 14:55:17 +02:00
996e1b7970
rfsom: constraint updates
2015-02-03 14:20:34 -05:00
fd2ab02174
cftl_std: Added in the constraint file comments regarding supported CFTLs
2015-01-29 16:27:43 +02:00
d69d105b5d
vc707_common: Fix address mapping
...
The axi_ethernet/eth_buf/S_AXI_2TEMAC address space and axi_ethernet/eth_mac/s_axi/Reg address
segment does not exist in 2014.4.
2015-01-29 12:22:06 +02:00
e8ff30119d
vc707_xdc: Delete unnecessary clock definition
2015-01-29 11:39:10 +02:00
6c8ea24f20
common: Update VC707 base design to 2014.4
2015-01-28 16:24:52 +02:00
e1d8dd10a9
daq2: Initial check in of the VC707 based project
...
NOTE: Can not communicate with the clock chip, rx/tx PLL not locking.
2015-01-28 16:24:06 +02:00
659e0cca4e
cftl_cip: Initial check in.
...
Project cftl_cip supports the following Circuits from the Lab pmods:
+ EVAL-CN0350-PMDZ
+ EVAL-CN0335-PMDZ
+ EVAL-CN0336-PMDZ
+ EVAL-CN0337-PMDZ
Note: Additional testing needed!
2015-01-23 18:29:32 +02:00
463a3bbc88
cftl_std: Updated project. Switched to PS7 gpio. Renamed signals.
2015-01-23 14:11:33 +02:00
9672271155
fmcjestadc1: a5gt: Updated project to work with linux and fixed ethernet
...
- added phy reset mechanism for proper functioning of the ethernet
- not all DDR is accesible, as NIOS2 can't access it with MMU enabled
2015-01-23 13:30:56 +02:00
5a77ab0161
a5gt:common: Added phy reset signal from ethernet in pin assignments
2015-01-23 12:31:41 +02:00
050f17e034
a5gt3: common: corrected naming in pin assignments. added reset signal from FPGA2
2015-01-23 12:30:16 +02:00
72e89852b6
daq2/kc705: 2014.4 updates
2015-01-14 12:58:08 -05:00
024d9e7309
replace export hardware -- hwdef/sysdef
2015-01-13 13:40:21 -05:00
03988f1c9f
kcu105-daq2-2014.4-- intermediate fixes
2015-01-13 13:40:20 -05:00
b595cce697
kcu105-daq2-2014.4-- intermediate fixes
2015-01-13 13:40:18 -05:00
b0b4bfe531
kcu105-daq2-2014.4-- intermediate fixes
2015-01-13 13:40:17 -05:00
47871287f3
kc705: Updated base project with linear flash. Updated all depending projects
2015-01-13 10:19:07 +02:00
b9e2c5659f
fmcomms2: 2014.4
2015-01-09 14:12:54 -05:00
9e64df917c
daq2: 2014.4
2015-01-09 14:12:53 -05:00
65d9f08763
zc706: mig 2014.4
2015-01-09 14:12:52 -05:00
868df1aac8
zc706: mig 2014.4
2015-01-09 14:12:51 -05:00
0258afbadc
board: add ddr seg variable
2015-01-09 14:12:50 -05:00
22d881981e
cftl_std: Renamed cftl standard project
2015-01-09 19:44:13 +02:00
debbe31713
Merge remote-tracking branch 'origin/master' into dev
2015-01-09 11:12:56 -05:00
117686f352
ad9739a: updates for ad9739a
2015-01-09 10:54:50 -05:00
785d3a4ae3
ad9739a: updates for ad9739a
2015-01-09 10:54:40 -05:00
e8d0782a2e
ad9739a: updates for ad9739a
2015-01-09 10:54:22 -05:00
baea2090d6
ad9739a: updates for ad9739a
2015-01-09 10:54:12 -05:00
c9b6411e86
ad9739a: updates for ad9739a
2015-01-09 10:54:00 -05:00
51e6d0888a
cftl_xil_zed: Initial commit for common platform used with CFTL circuits
...
This common platform uses PS7 SPI and I2C to communicate with different chips.
On different connectors different pin configurations are supported:
- On connector JA, a spi interface and a 2 pin GPIO
- On connector JB, a I2C interface
- On connector JC, a spi interface with 2 chip selects
2015-01-09 17:47:29 +02:00
a9cc8f6c91
ad9739a_fmc: added
2015-01-08 10:35:59 -05:00
a170ebfb82
imageon: Initial commit
...
Initial commit of the IMAGEON project for ZC706. NOT tested.
2015-01-08 17:01:22 +02:00
f566268db5
zed_common: Updated common to 2014.4
2015-01-08 11:59:26 +02:00
f6df66ea06
motcon2_fmc: initial commit of the base design
...
Because vivado crashes when adding the speed detector, it's not part of this commit.
The controller is also not part of this commit
2015-01-08 11:57:22 +02:00
eb569b991d
dmafifo- remove util fifo setup
2015-01-06 16:23:14 -05:00
9e707d8a33
rfifo: wrapper updates
2015-01-06 16:17:33 -05:00
a944deebd5
wfifo: wrapper updates
2015-01-06 16:17:25 -05:00
d2baf17ff0
rfsom: updated to rfsom
2014-12-23 14:04:02 -05:00
3d1ba585ee
rfsom: updated to rfsom
2014-12-23 14:04:01 -05:00
19c2da836c
rfsom: updated to rfsom
2014-12-23 14:03:59 -05:00
61ba4f4357
rfsom: updated to rfsom
2014-12-23 14:03:58 -05:00
614dfcd93c
rfsom: updated to rfsom
2014-12-23 14:03:57 -05:00
4b571ded8f
fmcomms2/rfsom: initial commit
2014-12-23 14:03:56 -05:00
ee52602c89
rfsom: initial commit
2014-12-23 14:03:55 -05:00
8e41af7b92
fmcomms2: 2014.4 update
2014-12-23 14:03:54 -05:00
0de1a38245
zc706: 2014.4 update
2014-12-23 14:03:52 -05:00
43037a42eb
scripts: 2014.4 update
2014-12-23 14:03:51 -05:00
71baa129a7
VC707: Fixed linear flash timings
2014-12-19 15:45:14 +02:00
2ff72d60d1
fmcomms2: Updated VC707 project to fix ethernet problem
2014-12-19 15:45:05 +02:00
4a9c4cdf19
fmcadc2_zc706: Fix PLDDR fifo name
2014-12-19 13:01:33 +02:00
6230cb25b7
fmcomms7_zc706: Add constraint file for PLDDR
2014-12-19 13:01:27 +02:00
6e124c4c24
fmcomms7_zc706: Connect PLDDR rst to external push button
2014-12-19 13:01:21 +02:00
a0b83bac7f
fmcomms7_zc706: Delete trailing spaces from system top
2014-12-19 13:01:15 +02:00
362b0f5300
daq3_zc706: Add constraint file for PLDDR
2014-12-19 13:01:10 +02:00
d77e28e372
daq3_zc706: Connect PLDDR rst to external push button
2014-12-19 13:01:05 +02:00
d483801e2d
daq3_zc706: Delete trailing spaces from system_top
2014-12-19 13:00:59 +02:00
df205f5cea
fmcadc2_zc706: Connect PLDDR rst to external push button
2014-12-19 13:00:53 +02:00
8fc1f046a4
fmcadc4_zc706: Add constraint file for PLDDR
2014-12-19 13:00:48 +02:00
7ec1e282d9
daq2_zc706: Add constraint file for the PLDDR
2014-12-19 13:00:42 +02:00
a6cf615ee0
zc706_constr: Move the sys_rst related constraint definition to zc706_system_mig_constr.xdc
2014-12-19 13:00:35 +02:00
153a4cef18
daq2: missing sys_rst decl.
2014-12-19 13:00:21 +02:00
ad144ef06a
plddr3: sys-rst from board pushbutton
2014-12-19 13:00:07 +02:00
33a8c8a155
plddr3: sys-rst from board pushbutton
2014-12-19 13:00:01 +02:00
0cc29fe03b
plddr3: sys-rst from board pushbutton
2014-12-19 12:59:54 +02:00
51bdcb1b12
plddr3: sys-rst from board pushbutton
2014-12-19 12:59:48 +02:00
daba3fb72e
plddr3: sys-rst from board pushbutton
2014-12-19 12:59:42 +02:00
758ac6bb8e
plddr3: sys-rst from board pushbutton
2014-12-19 12:59:35 +02:00
1a9eb8196a
VC707: Fixed linear flash timings
2014-12-18 17:49:00 +02:00
23e2886b5d
fmcadc2_zc706: Fix PLDDR fifo name
2014-12-18 16:57:19 +02:00
b684c8bf33
fmcomms7_zc706: Add constraint file for PLDDR
2014-12-18 10:15:11 +02:00
Istvan Csomortani
Rejeesh Kutty
Adrian Costina
Lars-Peter Clausen
dbogdan